Semiconductor Device Element Isolation Structure
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Solution Overview
Problem
In NAND-type flash memory devices, the use of polysilazane (PSZ) films for element isolation in peripheral circuit sections leads to crystal defects in low-voltage (LV) transistor regions due to high contraction stress, while reducing the depth of shallow trench isolation (STI) to alleviate this issue results in STI inversion leakage in high-voltage (HV) transistor regions.
Innovation Solution
The semiconductor device employs different thicknesses for gate insulating films in LV and HV transistor regions, with the LV region having a thinner gate insulating film and a shallower STI to reduce contraction stress and prevent crystal defects, and the HV region maintaining a thicker STI to minimize inversion leakage, allowing for distinct element isolation structures between the regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If PSZ film is used to fill the trench for forming embedded element isolation insulating film in peripheral circuit section, then coverage characteristics are improved, but crystal defects occur in LV transistor region due to high contraction stress
Solution Approach 1:
The patent applies different element isolation structures to different transistor regions: LV transistor regions use shallow trenches with reduced PSZ film depth to minimize contraction stress and prevent crystal defects, while HV transistor regions use deep trenches with full PSZ film depth to ensure proper isolation and prevent inversion leakage. This local differentiation resolves the contradiction by optimizing each region for its specific requirements.
2Ease of manufacture
If same element isolation structure is used in both LV and HV transistor regions, then manufacturing process is simplified, but cannot simultaneously prevent crystal defects in LV region and inversion leakage in HV region
Solution Approach 1:
The patent differentiates element isolation structures between LV and HV transistor regions by controlling PSZ film deposition depth: shallow depth in LV regions to prevent crystal defects, and full depth in HV regions to prevent inversion leakage. This local optimization achieves both reliability goals while maintaining relatively simple manufacturing through selective etching and deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces crystal defects in the LV transistor region and minimizes STI inversion leakage in the HV transistor region, enhancing the reliability and performance of the NAND-type flash memory by optimizing the element isolation structures for each voltage type.
Implementation Method 1
the PSZ film has the property of being high in contraction stress
Data Source
AI summary
A semiconductor device includes a plurality of first MOS transistors has a first gate electrode formed on a first gate insulating film provided in a first transistor region on a semiconductor substrate, a plurality of second MOS transistors has a second gate electrode formed on a second gate insulating film which is provided in a second transistor region on the semiconductor substrate and which is smaller in thickness than the first gate insulating film, a first element isolation region in the first transistor region, the first element isolation region provided between the plurality of first MOS transistors, and a second element isolation region in the second transistor region, the second element isolation region provided between the plurality of second MOS transistors. The upper surface of the second element isolation region is lower than the upper surface of the first element isolation region.