Semiconductor Isolation Region Layout for HVIC Reliability

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional high-voltage integrated circuit devices (HVICs) face challenges in achieving stable operation and long-term reliability due to parasitic resistances and electric field concentration, which affect chip size, layout constraints, and breakdown voltage, particularly in self-shielding schemes using high-voltage junctions.

Innovation Solution

The semiconductor integrated circuit device employs a self-shielding scheme with a high-voltage junction termination region, utilizing a p-type isolation region with a U-shaped, T-shaped, or L-shaped layout to reduce parasitic resistances and electric field concentration, and incorporates field plates to enhance breakdown voltage reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional self-shielding scheme using high-voltage junctions is employed, then electric potential insulation is achieved, but parasitic resistances increase and electric field concentration occurs, affecting breakdown voltage and reliability

Engineering Contradiction:

Improvebreakdown voltage and long-term reliabilityVSAvoidparasitic resistances and electric field concentration

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The isolation region is divided into a first isolation region and a second isolation region that are spatially separated. The first isolation region is positioned closer to the high-voltage junction, while the second isolation region is positioned farther away. This segmentation allows each region to serve distinct functions: the first region primarily handles electric field termination, while the second region focuses on parasitic resistance reduction, thereby resolving the contradiction between reliability improvement and harmful factor reduction.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A potential well structure is introduced as an intermediary element between the high-voltage junction and the isolation regions. This potential well acts as a mediator that redistributes the electric field more uniformly, reducing electric field concentration at critical interfaces. By introducing this intermediary structure, the patent achieves better electric field management without compromising the insulation function of the isolation regions.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If the isolation region is positioned closer to the high-voltage junction, then breakdown voltage is improved, but parasitic resistances increase

Engineering Contradiction:

Improvebreakdown voltageVSAvoidparasitic resistances

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

3Object-generated harmful factors

If the isolation region is positioned farther from the high-voltage junction, then parasitic resistances are reduced, but breakdown voltage decreases

Engineering Contradiction:

Improveparasitic resistancesVSAvoidbreakdown voltage

Core Design Contradiction:

Object-generated harmful factorsVSReliability

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

4Reliability

If a conventional isolation layout is used, then electric potential insulation is maintained, but chip size increases and layout flexibility decreases

Engineering Contradiction:

Improveelectric potential insulationVSAvoidchip size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a conventional planar isolation layout to a three-dimensional stacked configuration. The first and second isolation regions are arranged in different vertical layers, allowing them to occupy different spatial dimensions. This dimensional change enables the isolation structure to maintain its insulation function while occupying less planar area on the chip, thereby reducing overall chip size and increasing layout flexibility.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10658504B2Semiconductor integrated circuit device

Publication Date: 2020.05.19 FUJI ELECTRIC CO LTD

AI summary

A p−-type isolation region is provided at a part between a p-type ground region and a circuit region (a high potential region and an intermediate potential region) in an n-type well region. The p−-type isolation region is electrically connected with a H-VDD pad and an n+-type drain region of a HVNMOS. The p−-type isolation region has between n+-type pickup connect regions and between n+-type drain regions of two of the HVNMOSs, a protruding part (a T-shaped part, an L-shaped part, a partial U-shaped part) or an additional part that protrudes toward a p-ground region.