Semiconductor Isolation Patterning With Selective Dielectric Deposition
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Solution Overview
Problem
The manufacturing of highly integrated and high-performance semiconductor devices is complicated and costly due to the complexity of device isolation layer formation and the need for fine patterns, which increases the manufacturing process complexity and costs.
Innovation Solution
A method involving the formation of multiple mask layers and spacer layers, followed by selective deposition and etching processes to create different pattern widths and densities in various regions of the semiconductor device, allowing for improved electrical properties and a simplified manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing processes are used for highly integrated semiconductor devices, then fine patterns can be achieved, but manufacturing complexity and costs increase
Solution Approach 1:
The manufacturing process is divided into multiple sequential patterning steps including forming first, second, and third spacer layers with different materials and thicknesses. Each spacer layer is formed through separate deposition and etching processes, allowing incremental pattern definition and enabling fine pattern formation while managing process complexity through systematic breakdown of the overall manufacturing sequence
Solution Approach 2:
The patent introduces vertical layering with multiple spacer layers deposited at different heights and depths. The first spacer layer is formed at a lower level, followed by a second spacer layer at a higher level, and a third spacer layer that bridges between them. This vertical dimensionality enables complex 3D pattern formation while maintaining control over each individual layer through separate process steps
2Reliability
If device isolation layer formation is implemented for highly scaled devices, then electrical isolation between unit devices is achieved, but manufacturing complexity increases
Solution Approach 1:
The first spacer layer is formed in advance as a preliminary structure before subsequent patterning steps. This preliminary spacer layer serves as a foundation for defining the device isolation regions, allowing the isolation structure to be pre-positioned and then refined through subsequent etching and spacer formation steps, thereby achieving reliable electrical isolation while simplifying the overall process sequence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor devices with improved electrical properties and reduced manufacturing complexity, achieving fine patterns and efficient device isolation with reduced costs.
Implementation Method 1
A second spacer layer is formed, which covers the first spacer layer on the second region exposed by the mask, using a selective dielectric-on-dielectric deposition process
Data Source
AI summary
A semiconductor device fabrication method includes forming a substrate having first and second regions therein, with different densities of active regions in the first and second regions. A cell trench is formed, which defines cell active regions in the first region, and a peripheral trench is formed, which defines peripheral active regions in the second region. A first insulating layer is formed in the cell trench and the peripheral trench. A mask is selectively formed, which covers the first insulating layer in the first region and exposes the first insulating layer in the second region. A second insulating layer is formed on the first insulating layer in the second region exposed by the mask, using a selective dielectric-on-dielectric deposition process. The first insulating layer is exposed in the first region by removing the mask. A third insulating layer is formed on the first insulating layer in the first region and on the second insulating layer in the second region.