Semiconductor Device Isolation Step Height Reduction
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Solution Overview
Problem
The existing semiconductor device fabrication method results in increased diffusion layer resistance and silicide thin-wire resistance due to the larger step height between the first shallow trench isolation region and the semiconductor substrate in the memory formation area, which also reduces the overlapping margins of contacts and diffusion layers.
Innovation Solution
The semiconductor device is configured such that the height of the top surface of the first isolation region in the memory formation area is made equal to or smaller than that of the second isolation region in the logic formation area by selectively removing the upper part of the first isolation region before forming the gate dielectric, thereby reducing the sidewall effect and maintaining the surface area of diffusion layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the first shallow trench isolation region is formed with a higher top surface than the semiconductor substrate to provide isolation, then the isolation effect is improved, but the step height increases causing sidewall formation that reduces diffusion layer surface area and increases resistance
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer (CMP layer) before forming the gate electrode. This planarization layer compensates for the step height between the first shallow trench isolation region and the semiconductor substrate, preventing sidewall formation during subsequent processing steps. The CMP layer is formed to a thickness that covers the step height, ensuring that the gate electrode can be formed without encountering the isolation region step, thereby preserving the full surface area of the diffusion layer for effective doping.
2Manufacturing precision
If the step height between the first shallow trench isolation region and the semiconductor substrate is reduced to maintain diffusion layer surface area, then the isolation effect is weakened, but the diffusion layer resistance is reduced
Solution Approach 1:
The patent introduces a planarization layer (CMP layer) as an intermediary between the first shallow trench isolation region and the gate electrode. This intermediary layer serves dual purposes: it maintains the high isolation effect by preserving the original step height of the shallow trench isolation region, while simultaneously planarizing the surface to prevent sidewall formation during gate electrode formation. The CMP layer acts as a buffer that decouples the isolation function from the surface topology, allowing both high isolation and full diffusion layer surface area to be achieved.
3Area of stationary object
If the gate electrode is formed to cover the stepped portion of the first shallow trench isolation region, then the gate coverage is improved, but sidewalls are formed on the stepped portions reducing the effective area
Solution Approach 1:
The patent applies preliminary action by forming the planarization layer (CMP layer) before depositing the gate electrode material. This planarization layer is specifically designed to cover the stepped portions of the first shallow trench isolation region, creating a flat surface for gate electrode formation. By doing so, the gate electrode can be formed with uniform thickness and proper coverage without encountering the isolation region steps, thereby preventing sidewall formation and preserving the full effective area of the diffusion layer for doping.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration prevents the increase in diffusion layer resistance and silicide thin-wire resistance, while maintaining the overlapping margins of contacts and diffusion layers, by ensuring the step height between the isolation region and the semiconductor substrate is minimized.
Implementation Method 1
a first gate dielectric that can store charges between the semiconductor region and the first gate electrode
Implementation Method 2
a gate dielectric 7 is formed on a part of the semiconductor substrate 1 located in the CMOS formation area 200 by thermal oxidation
Data Source
AI summary
A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.