Semiconductor Isolation Structure with Equipotential Terminal

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Solution Overview

Problem

Existing semiconductor isolation structures, such as shallow trench isolation (STI) and deep trench isolation (DTI), are not fully satisfactory and can limit the performance of semiconductor devices under certain conditions, particularly in terms of voltage isolation and reliability, especially when subjected to backside bias voltage and external voltage interference.

Innovation Solution

A semiconductor device design featuring two isolation structures with a terminal equipotential to the source, positioned between them, to mitigate interference from external voltages and enhance reliability, including a doped region with different conductivity types and additional isolation structures to optimize spacing and reduce leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single isolation structure is used, then the device structure is simple, but voltage isolation and reliability are insufficient under backside bias voltage

Engineering Contradiction:
Improvevoltage isolation and reliabilityVSAvoidisolation structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The isolation structure is divided into two distinct parts: a first isolation structure surrounding the doped region and a second isolation structure surrounding the first isolation structure with spacing between them. This segmentation allows each isolation structure to perform specific functions - the first provides local isolation and the second provides external voltage shielding - thereby improving overall voltage isolation and reliability without using a single overly complex structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first isolation structure is nested within the second isolation structure, with the first isolation structure positioned inside the region surrounded by the second isolation structure. This nested configuration creates multiple isolation barriers, where the outer second isolation structure shields against external voltage interference while the inner first isolation structure provides local isolation, significantly enhancing voltage isolation performance.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Area of stationary object

If isolation structures are placed close together, then device area is reduced, but leakage current increases due to voltage interference

Engineering Contradiction:
Improvedevice areaVSAvoidleakage current
Core Design Contradiction:
Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

A terminal equipotential to the source is introduced as an intermediary element positioned between the first and second isolation structures. This terminal acts as a mediator that shields the doped region from external voltage interference by maintaining equipotential conditions. The intermediary terminal allows the isolation structures to be placed closer together while preventing voltage interference that would otherwise cause leakage current, thus reducing device area without increasing leakage.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Length of moving object

If the terminal is positioned close to the doped region, then spacing is minimized, but external voltage interference increases

Engineering Contradiction:
Improvespacing between structuresVSAvoidexternal voltage interference
Core Design Contradiction:
Length of moving objectVSObject-affected harmful factors

Solution Approach 1:

The spacing between the first and second isolation structures is made asymmetric by positioning the terminal equipotential to the source at a specific location between them. The terminal is positioned closer to one isolation structure than the other, creating an asymmetric configuration that optimizes the shielding effect. This asymmetric positioning allows minimal overall spacing while the terminal strategically blocks external voltage interference from reaching the doped region.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS10396196B1Semiconductor devices
Publication Date: 2019.08.27 VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
  • US10396196B1 patent drawing
  • US10396196B1 patent drawing
  • US10396196B1 patent drawing

AI summary

A semiconductor device includes a substrate, a semiconductor layer, a doped region, a device region, a first isolation structure, a second isolation structure and a terminal. The semiconductor layer is disposed over the substrate. The doped region is disposed in the semiconductor layer. The device region is disposed on the doped region and includes a source, a drain and a gate. The first isolation structure is disposed in the semiconductor layer and surrounds the doped region. The second isolation structure surrounds the first isolation structure and is spaced apart from the first isolation structure. The terminal is disposed between the first isolation structure and the second isolation structure, and is equipotential with the source.