Semiconductor Isolation Structure for Memory Array Toppling Prevention
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Solution Overview
Problem
The existing semiconductor manufacturing methods fail to effectively prevent memory array toppling by providing adequate support to active areas in memory devices, leading to potential structural instability and performance issues.
Innovation Solution
A manufacturing method that forms a U-shaped blocking structure between the central and peripheral regions of a semiconductor substrate using a combination of dielectric layers and a sacrificial layer, where the blocking structure is made of a material with a higher dielectric constant than the insulation structure, and is designed to expand during annealing to prevent toppling, while the insulation structure provides electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a simple insulation structure is formed between central and peripheral regions, then manufacturing process is simple, but the active areas cannot be adequately supported and may topple
Solution Approach 1:
The isolation structure is divided into multiple functional layers: a first dielectric layer for basic insulation, a second dielectric layer with higher dielectric constant for enhanced support, and a sacrificial layer for creating the U-shaped blocking structure. This segmentation allows each layer to perform its specific function, providing adequate support strength while maintaining manufacturing feasibility through standardized layer-by-layer fabrication processes.
Solution Approach 2:
The patent employs composite dielectric materials with different dielectric constants in the isolation structure. The first dielectric layer uses a material with lower dielectric constant for electrical isolation, while the second dielectric layer uses a material with higher dielectric constant to provide mechanical support. This composite approach enables the structure to simultaneously achieve electrical isolation and mechanical support functions without excessive complexity.
2Strength
If the blocking structure is made with material having higher dielectric constant, then active areas are better supported, but electrical isolation between regions may be compromised
Solution Approach 1:
The patent applies local quality by assigning different dielectric constant characteristics to different spatial regions of the isolation structure. The first dielectric layer, positioned closer to the active areas, uses material with lower dielectric constant to ensure electrical isolation. The second dielectric layer, positioned deeper in the trench, uses material with higher dielectric constant to provide mechanical support. This spatial differentiation of material properties allows simultaneous achievement of electrical isolation and mechanical support functions.
3Manufacturing precision
If the filling material is annealed at high temperature to cure it, then the filling material shrinks and may cause toppling, but without annealing the filling material is not properly formed
Solution Approach 1:
The patent exploits differential thermal expansion behavior during annealing. The blocking structure is designed with specific dimensional relationships that account for the shrinkage of the filling material during high-temperature annealing. The U-shaped configuration and spacing of the blocking structure are calculated to maintain adequate support even after the filling material shrinks, preventing toppling while ensuring proper material formation through the necessary annealing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively prevents active areas from toppling and ensures electrical isolation between regions, enhancing the structural integrity and performance of memory devices by using a blocking structure that expands less than the filling material during high-temperature processing.
Implementation Method 1
the blocking structure expands during annealing the filling material layer and the filling material layer shrinks during annealing the filling material layer
Data Source
AI summary
A manufacturing method of a semiconductor device including providing a substrate, forming a hard mask over the substrate, etching the substrate by using the hard mask as an etch mask to form a first protrusion region and a plurality of second protrusion regions, wherein the first protrusion region is separated from a closest one of the second protrusion regions by a first trench, and neighboring two of the second protrusion regions are separated by a second trench, forming a first dielectric layer lining the first trench and the second trench, forming a second dielectric layer in the first trench, in which the second dielectric layer is along the first dielectric layer in the first trench, etching back the second dielectric layer to form a blocking structure, and filling the first trench with a filling material, in which the filling material covers the blocking structure.