Semiconductor Isolation Structure with Undercut for Leakage Reduction
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Solution Overview
Problem
Conventional deep trench isolation methods in semiconductor fabrication lead to etch damage and physical defects, such as voids, causing electric current leakage between devices integrated on a single chip, which complicates the design and increases the risk of malfunctions.
Innovation Solution
A semiconductor isolation structure is developed using a two-step etching process to form a deep trench, followed by the sequential deposition and annealing of oxide layers, and filling with a polysilicon filler, which reduces etch damage and physical defects, and includes an undercut structure to minimize leakage and stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a deep trench is formed using polishing process, then the trench isolation structure is created, but etch damage is done to the semiconductor substrate and defect areas are formed on the surface
Solution Approach 1:
The patent extracts and removes the harmful polishing process from the trench formation method. Instead of using mechanical polishing that causes etch damage and defects, the invention uses a chemical etching process that forms the trench without direct mechanical contact, thereby eliminating the source of substrate damage while still achieving the required trench isolation structure.
Solution Approach 2:
The patent replaces the mechanical polishing system with a chemical etching system. The mechanical action of polishing that causes damage is substituted by a chemical reaction process using etchants that selectively remove material to form the trench, eliminating mechanical stress and physical damage to the substrate while achieving the same isolation function.
2Reliability
If the deep trench isolation structure is formed adjacent to a device receiving high bias, then the isolation function is provided, but the leak electric current increases due to difficulty in designing appropriate thickness or processing conditions
Solution Approach 1:
The patent changes the critical parameters of the trench isolation structure, specifically optimizing the trench depth, oxide layer thickness, and etching conditions to achieve minimal leakage current. By carefully controlling these parameters—such as forming the oxide layer to a specific thickness range and adjusting the etching depth—the invention reduces leak electric current while simplifying the design process for high-bias devices.
Solution Approach 2:
The patent performs preliminary oxidation before trench filling to create a protective oxide layer that prevents leakage current. This preliminary action of forming the oxide barrier layer in advance addresses potential leakage issues before the trench is filled, eliminating the need for complex post-processing adjustments and simplifying the overall design for high-bias device isolation.
3Ease of manufacture
If a conventional technique is used for fabricating device isolation, then the process is simplified, but there is a high risk of causing physical defects such as voids in the semiconductor device
Solution Approach 1:
The patent applies beforehand cushioning by forming a protective oxide layer and using controlled etching processes that prevent void formation. The oxide layer acts as a cushioning barrier that prevents direct contact between the filling material and the substrate, eliminating the risk of voids and other physical defects while maintaining fabrication process simplicity through a systematic sequence of protective steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces electric current leakage and minimizes physical defects, enhancing the reliability of semiconductor devices by reducing etch damage and stress during the fabrication process.
Implementation Method 1
an oxide layer which is formed on an inner sidewall and a bottom surface of the trench
Implementation Method 2
an oxide layer which is formed on an inner sidewall and a bottom surface of the trench
Implementation Method 3
sequential deposition and annealing of oxide layers
Data Source
AI summary
An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer.