Semiconductor Packaging Jig With Elastic Support for Precise Assembly

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Solution Overview

Problem

The integration of multiple semiconductor devices into compact, high-performance packages poses challenges in achieving miniaturization, reduced transmission and insertion loss, and efficient electrical performance, particularly in the context of wafer-level packaging for electronic devices like cell phones.

Innovation Solution

The development of a semiconductor package manufacturing process involving a carrier with a redistribution layer, semiconductor bridges, and testing structures, including TIVs and encapsulants, to facilitate the integration and interconnection of semiconductor dies, along with the use of jigs for precise assembly and metallization, enabling efficient electrical connections and thermal management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If multiple semiconductor devices are integrated into compact packages, then miniaturization and electrical performance are improved, but manufacturing complexity and assembly difficulty increase

Engineering Contradiction:
Improvepackage sizeVSAvoidmanufacturing complexity
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The manufacturing process is divided into distinct stages: wafer-level processing, die separation, individual die packaging, and final assembly. Each stage handles specific tasks independently, allowing complex multi-die packages to be built from simpler intermediate structures without overwhelming manufacturing complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from traditional planar 2D packaging to three-dimensional vertical stacking of multiple semiconductor dies. This dimensional change enables compact package volumes while maintaining electrical performance through vertical interconnections, resolving the contradiction between miniaturization and manufacturing complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If wafer-level packaging is used, then manufacturing efficiency is improved, but precision control during assembly becomes more difficult

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidassembly precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

Semiconductor dies are pre-processed and prepared on the wafer level before separation, including metallization, encapsulation, and initial testing. This preliminary action ensures that when dies are later assembled into packages, the critical precision requirements are already satisfied, allowing high manufacturing efficiency without sacrificing assembly precision

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces intermediate carrier structures and alignment fixtures that mediate between the wafer-level processing stage and final package assembly. These intermediaries maintain precise positioning information through the manufacturing process, enabling both high productivity and manufacturing precision

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of energy

If electrical connection lengths are reduced, then transmission loss and insertion loss are improved, but packaging structure becomes more complex

Engineering Contradiction:
Improvetransmission lossVSAvoidpackaging structure
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent implements vertical stacking of semiconductor dies with direct vertical interconnections through the package structure. This three-dimensional arrangement dramatically reduces electrical connection lengths compared to traditional planar layouts, minimizing transmission and insertion loss. The vertical architecture naturally accommodates multiple dies while keeping interconnect paths short, resolving the contradiction between reduced loss and structural complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240387446A1Jig for manufacturing semiconductor package
Publication Date: 2024.11.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240387446A1 patent drawing
  • US20240387446A1 patent drawing
  • US20240387446A1 patent drawing

AI summary

A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.