Semiconductor Package Joint Structure for Crack-Resistant Stacking
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Solution Overview
Problem
The challenge of joining multiple semiconductor packages in a limited space within electronic devices, such as mobile phones and fitness trackers, is exacerbated by cracks and delamination at the interfaces due to mechanical property differences, which reduces the reliability of the semiconductor devices.
Innovation Solution
The implementation of adhesion layers, such as titanium and chromium layers, in direct contact with semiconductor packages, combined with a die attach film having slanted sidewalls, ensures better adhesion and reduces cracks, enhancing the reliability of the joint between semiconductor packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor packages are joined in a limited space, then device integration is improved, but cracks and delamination occur at interfaces due to mechanical property differences
Solution Approach 1:
An adhesion layer is introduced as an intermediary between the semiconductor package and the die attach film. This adhesion layer serves as a mediator that bridges the mechanical property differences between the rigid semiconductor package and the flexible die attach film, preventing stress concentration and interface failure while enabling reliable multi-package stacking.
Solution Approach 2:
The patent employs a composite structure consisting of multiple materials with different mechanical properties: the semiconductor package substrate, the adhesion layer with intermediate mechanical properties, and the die attach film. This composite material system gradually transitions mechanical properties across the interface, reducing stress concentration and preventing cracks and delamination.
2Reliability
If adhesion layers are added to improve bonding, then interface reliability is improved, but device complexity increases
Solution Approach 1:
The bonding interface is segmented into distinct functional layers: the semiconductor package substrate, the adhesion layer, and the die attach film. This segmentation allows each layer to be optimized for its specific function while maintaining overall simplicity. The adhesion layer is applied only at critical interface regions rather than uniformly across the entire device.
Solution Approach 2:
The adhesion layer is strategically positioned at the interface between the semiconductor package and die attach film where mechanical stress concentration occurs. This localized application provides enhanced bonding precisely where needed without adding unnecessary complexity to other regions of the device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability of semiconductor devices by reducing cracks and delamination, allowing for more robust bonding and efficient use of space in electronic devices.
Implementation Method 1
The implementation of adhesion layers, such as titanium and chromium layers, in direct contact with semiconductor packages
Implementation Method 2
a die attach film having slanted sidewalls, ensures better adhesion and reduces cracks
Data Source
AI summary
The present disclosure describes a structure that joins semiconductor packages and a method for forming the structure. The structure includes an adhesion layer in contact with a first semiconductor package and a first joint pad in contact with the adhesion layer. The structure further includes a film layer disposed on the first semiconductor package and the first joint pad, where the film layer includes a slanted sidewall, the slanted sidewall covers an end portion of the adhesion layer and a first portion of the first joint pad, and the slanted sidewall exposes a second portion of the first joint pad. The structure further includes a solder ball attached to the second portion of the first joint pad and a second joint pad of a second semiconductor package.