Semiconductor Junction Structure for Lower Recovery Current
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Solution Overview
Problem
Semiconductor devices, such as MOSFETs, face challenges in reducing power consumption due to high recovery currents and surge voltages, which are associated with long carrier lifetimes in junction regions, leading to increased power consumption and noise in electrical devices.
Innovation Solution
The semiconductor device incorporates a junction region with a higher concentration of a first element, such as platinum, and a specific structure where the carrier lifetime is shorter in the junction region compared to other regions, reducing the recovery current and surge voltage by controlling the diffusion of the element and adjusting the density of traps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the carrier lifetime in the junction region is extended to improve charge storage capacity, then the power consumption increases due to higher recovery currents and surge voltages
Solution Approach 1:
The patent applies local quality by creating distinct regions with different carrier lifetimes within the semiconductor device. Specifically, the junction region is designed with a shorter carrier lifetime compared to other regions, allowing localized optimization where charge storage is reduced in the junction region while maintaining adequate storage in other areas. This resolves the contradiction by enabling sufficient accumulated charge overall while minimizing recovery current and power consumption in the critical junction region.
Solution Approach 2:
The patent employs parameter changes by systematically varying the carrier lifetime parameter across different regions of the semiconductor device. By adjusting the carrier lifetime to be shorter in the junction region compared to other regions, the patent optimizes the balance between charge storage capacity and power consumption. This parameter optimization reduces recovery currents and surge voltages while maintaining necessary charge accumulation for device operation.
2Quantity of substance
If the carrier lifetime in the junction region is extended to improve charge storage, then the surge voltage and noise increase leading to electrical interference
Solution Approach 1:
The patent applies local quality by creating distinct regions with different carrier lifetimes within the semiconductor device. Specifically, the junction region is designed with a shorter carrier lifetime compared to other regions, allowing localized optimization where charge storage is reduced in the junction region while maintaining adequate storage in other areas. This resolves the contradiction by enabling sufficient accumulated charge overall while minimizing recovery current and power consumption in the critical junction region.
Solution Approach 2:
The patent employs parameter changes by systematically varying the carrier lifetime parameter across different regions of the semiconductor device. By adjusting the carrier lifetime to be shorter in the junction region compared to other regions, the patent optimizes the balance between charge storage capacity and power consumption. This parameter optimization reduces recovery currents and surge voltages while maintaining necessary charge accumulation for device operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption by minimizing the accumulated charge and recovery current, while also reducing surge voltage and noise in the electrical device, by strategically managing the carrier lifetime and trap density within the semiconductor device's regions.
Implementation Method 1
a concentration of a first element in the junction region is greater than a concentration of the first element in a first semiconductor region and greater than a concentration of the first element in a fourth semiconductor region
Implementation Method 2
a density of traps in the junction region is greater than a density of traps in the first semiconductor region and greater than a density of traps in the fourth semiconductor region
Data Source
AI summary
According to one embodiment, a semiconductor device includes first and second electrodes, first, fourth, and sixth semiconductor regions of a first conductivity type, a junction region, a fifth semiconductor region of a second conductivity type, and a gate electrode. The junction region includes a second semiconductor region of the first conductivity type and a third second semiconductor region of the second conductivity type. The second semiconductor regions and the third semiconductor regions are alternately provided in a second direction perpendicular to a first direction. A concentration of at least one first element selected from the group consisting of a heavy metal element and a proton in the junction region is greater a concentration of the first element in the fourth semiconductor region, or a density of traps in the junction region is greater than that in the first semiconductor region and greater than that in the fourth semiconductor region.