Semiconductor Key Pattern Formation via Spacer Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in forming defect-free key patterns, which can lead to voids and alignment issues, affecting the reliability and performance of semiconductor devices.
Innovation Solution
A method involving the formation of sacrificial patterns, spacer layers, and anisotropic etching to create spacers and trenches, allowing for the alignment of contact plugs using defect-free key patterns, with specific layer thickness and spacing configurations to prevent voids and ensure accurate alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional key pattern formation methods are used, then the fabrication process is simple, but voids and defects occur in the key patterns
Solution Approach 1:
The fabrication process is divided into multiple sequential stages: forming sacrificial patterns, depositing spacer layers, anisotropic etching to create spacers, removing sacrificial patterns, and filling trenches. Each stage produces a specific intermediate structure that enables the final defect-free key patterns, breaking down the complex formation process into manageable segments.
Solution Approach 2:
Sacrificial patterns are formed in advance before the actual key pattern formation. These preliminary structures serve as templates that guide subsequent spacer deposition and etching processes, ensuring precise positioning and preventing defects in the final key patterns.
2Measurement precision
If key patterns are formed without proper alignment structures, then the fabrication process is faster, but contact plug alignment is inaccurate
Solution Approach 1:
Spacer structures serve as intermediary alignment references between the substrate and contact plugs. These spacers are precisely positioned relative to transistor gates and provide visual or physical references for aligning contact plugs, ensuring accurate positioning without requiring complex real-time measurement systems.
Solution Approach 2:
The alignment system extends from two-dimensional planar patterns to three-dimensional spacer structures with vertical height. This additional dimensional information provides better contrast and reference points for alignment, improving precision while maintaining fabrication efficiency through standard lithography and etching processes.
3Length of moving object
If spacer layer thickness is reduced to achieve smaller features, then feature size decreases, but void formation increases
Solution Approach 1:
The method optimizes the relationship between spacer layer thickness and etching depth parameters. By carefully controlling the spacer thickness to be sufficient for complete sacrificial pattern removal while maintaining appropriate aspect ratios, the process achieves small key pattern widths without creating voids. The etching parameters are adjusted to match the spacer dimensions, ensuring complete material removal and void-free filling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of reliable semiconductor devices with improved alignment and reduced defects, enhancing the performance and reliability of semiconductor devices by ensuring precise key pattern formation and contact plug alignment.
Implementation Method 1
anisotropically etching the spacer layer to form spacers at both sides of the sacrificial patterns
Data Source
AI summary
Provided are a method of forming key patterns and a method of fabricating a semiconductor device using the same. The method of forming key patterns may include forming gate and key patterns on a cell region and a scribe lane region, respectively. Here, the key patterns may be formed to have a large width and a larger pitch than those of the gate patterns.