Semiconductor Package L-Shaped Pad Offset for Thickness Reduction
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Solution Overview
Problem
Existing semiconductor packages with stacked chips face challenges in minimizing size and manufacturing complexity due to overlapping pad arrangements, leading to increased thickness and manufacturing costs.
Innovation Solution
A semiconductor package design with a package substrate and stacked semiconductor chips of the same type, featuring L-shaped pad arrangements where upper chips are offset to avoid overlapping, using thin adhesive members and auxiliary connectors for efficient connection, allowing for single curing and simplified wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional stacked chip design with overlapping pad arrangements is used, then chip stacking is achieved, but package thickness increases and manufacturing complexity increases
Solution Approach 1:
The patent applies asymmetry by implementing an L-shaped pad arrangement where the first chip has pads along its first side and the second chip has pads along its second side, which is offset relative to the first chip. This asymmetric configuration allows the second chip to be positioned such that its pad arrangement does not overlap with the first chip's pad arrangement, thereby reducing package thickness and simplifying manufacturing processes while maintaining functional connectivity.
2Volume of moving object
If conventional stacked chip design with overlapping pad arrangements is used, then chip stacking is achieved, but package thickness increases
Solution Approach 1:
The L-shaped pad arrangement with offset positioning creates an asymmetric structure where the second chip is deliberately positioned to avoid overlapping the first chip's pads. This asymmetric layout reduces the vertical space required (package thickness) while the systematic offset pattern keeps the pad arrangement manageable and manufacturable.
3Volume of moving object
If thin adhesive members are used to minimize package thickness, then package thickness is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements preliminary action by pre-defining the offset positioning relationship between the first and second chips in the L-shaped pad arrangement design stage. This predetermined offset configuration allows thin adhesive members to be used effectively, as the alignment requirements are built into the design geometry rather than requiring high-precision adjustment during assembly, thereby reducing package thickness without excessively increasing manufacturing precision demands.
Data Source
AI summary
A semiconductor package includes a package substrate, semiconductor chips stacked on the package substrate, and electrical connectors that connect internal circuitry of each of the chips to the package substrate. Each of the semiconductor chips includes a chip selection pad for transmitting a chip selection signal to the internal circuitry of the semiconductor chip and a chip dummy pad, electrically isolated from the internal circuitry, along a first side of the semiconductor chip. The electrical connectors include a lower chip connector that electrically connects the package substrate to the chip selection pad of the lower semiconductor chip, a first auxiliary connector that electrically connects the package substrate to the chip dummy pad of the lower semiconductor chip, and a second auxiliary connector that electrically connects the chip dummy pad of the lower semiconductor chip to the chip selection pad of the upper semiconductor chip.