Semiconductor Device Ladder Interconnection Reduces On-State Resistance
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Solution Overview
Problem
Existing semiconductor devices, such as MOSFETs and IGBTs, face challenges in achieving high breakdown capability with low power dissipation and low saturation voltage, as well as efficient switching speed due to narrow channel portions leading to increased on-state resistance and saturation voltage.
Innovation Solution
The semiconductor device incorporates a first base layer of high resistivity with a collector or drain layer of a second conductivity type, a second base layer, an emitter or source layer, and a base contact layer with higher impurity density, featuring gate electrodes and insulating films within trenches that extend into intermediate depths, and includes additional emitter or source layers extending perpendicular to form a ladder interconnection, allowing for increased contact area and reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the second base layer is formed as a set of p regions with narrow channel portions to increase breakdown capability, then the breakdown voltage is improved, but the on-state resistance increases and saturation voltage increases
Solution Approach 1:
The patent introduces a base contact layer extending in the depth direction (third dimension) beneath the narrow-channel second base layer. This vertical extension provides additional low-resistance current paths without increasing the horizontal channel width, thus maintaining breakdown capability while reducing on-state resistance through the added dimensional pathway.
Solution Approach 2:
The base contact layer acts as an intermediary structure between the second base layer and the collector layer. It provides a low-resistance connection path that mediates the current flow, reducing the overall on-state resistance without affecting the narrow channel geometry that enables high breakdown voltage.
2Strength
If the channel portions are made narrow to increase breakdown voltage, then the breakdown capability is improved, but the switching speed decreases
Solution Approach 1:
By extending the base contact layer in the depth direction, the patent creates additional current paths that do not interfere with the narrow horizontal channel. This allows fast switching through improved carrier extraction via the vertical contact paths while preserving the high breakdown voltage achieved by the narrow channel structure.
Solution Approach 2:
The base contact layer is segmented into multiple regions corresponding to different emitter regions, allowing independent optimization of current extraction paths. This segmentation enables faster switching by providing multiple parallel pathways for carrier removal without compromising the narrow channel breakdown characteristics.
3Loss of energy
If the on-state resistance is reduced by widening channel portions, then the power dissipation is improved, but the breakdown capability decreases
Solution Approach 1:
The base contact layer extends in the depth direction to provide additional current paths perpendicular to the channel direction. This allows reduction of on-state resistance through the vertical contact paths without increasing the horizontal channel width, thus maintaining the high breakdown capability while reducing power dissipation.
4Loss of energy
If the base contact layer is added with higher impurity density to reduce base resistance, then the on-state resistance is improved, but the device complexity increases
Solution Approach 1:
The base contact layer is merged with the collector layer structure, forming an integrated region that serves both as a structural support and a low-resistance current path. This merging reduces the need for separate complex contact structures while achieving the goal of reduced base resistance.
Data Source
AI summary
A p-type collector layer is formed on a reverse side of an n-type high-resistivity first base layer, a p-type second base layer is formed on an obverse side of the first base layer, an emitter layer is formed on the second base layer, gate electrodes are formed inside trenches extending in a direction and intruding through the emitter layer and the second base layer into intermediate depths of the first base layer, with gate insulating films in between, a collector electrode is connected to the collector layer, an emitter electrode is connected to the emitter layer, the first base layer and the second base layer, the emitter layer is composed of first emitter layers extending along the trenches in the direction, and second emitter layers extending in a perpendicular direction for a ladder form interconnection between first emitter layers, and the base contact layer has a higher impurity density than the second base layer, and envelopes the second emitter layers.