Semiconductor Laminar Structure with Protective Layer for Stress Management
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Solution Overview
Problem
Semiconductor components face stress-related bending or cracking issues due to lattice and thermal expansion coefficient mismatches between substrates and epitaxial layers, leading to reduced yield and high manufacturing costs, particularly with silicon and sapphire substrates.
Innovation Solution
A laminar structure with a protective layer made of metal silicide or polysilicon, having thermal expansion coefficients greater or less than the silicon substrate, is introduced to absorb and release stress, reducing lattice mismatch and enabling low-temperature processing, thereby minimizing bending and cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a silicon substrate is used for GaN epitaxial growth, then manufacturing cost is reduced, but stress-induced bending and cracking occur due to lattice and thermal expansion mismatch
Solution Approach 1:
A protective layer made of metal silicide or polysilicon is introduced as an intermediary between the silicon substrate and the GaN epitaxial layer. This protective layer has thermal expansion coefficient matched to GaN and provides a buffer that reduces stress transmission from the silicon substrate, preventing bending and cracking while enabling the use of low-cost silicon substrates
Solution Approach 2:
The thermal expansion coefficient parameter is carefully selected for the protective layer material (metal silicide or polysilicon) to match GaN's thermal expansion characteristics. This parameter matching creates a stress-buffering interface that decouples the thermal expansion mismatch between silicon substrate and GaN epitaxial layer, allowing cost-effective silicon substrates to be used without sacrificing yield
2Manufacturing precision
If a buffer layer is added to reduce lattice mismatch, then epitaxial layer quality improves, but manufacturing complexity and cost increase due to high-temperature crystal growth requirements
Solution Approach 1:
The protective layer is designed as a simpler, more robust structure compared to traditional buffer layers. It can be formed using lower-temperature processes (metal silicide deposition or polysilicon deposition) rather than requiring high-temperature crystal growth, reducing manufacturing complexity while still providing effective stress management
Solution Approach 2:
The complex high-temperature crystal growth process required for traditional buffer layers is replaced with simpler deposition processes for forming the protective layer. The stress management function is achieved through material selection (metal silicide or polysilicon with matched thermal expansion) rather than through complex crystal structure engineering
3Manufacturing precision
If sapphire substrate is used instead of silicon, then lattice mismatch is reduced, but manufacturing cost increases and thermal expansion mismatch remains
Solution Approach 1:
The protective layer serves as an intermediary that decouples the interface between substrate and epitaxial layer. It provides thermal expansion matching with GaN while allowing the use of silicon substrates, achieving effective stress management without requiring expensive sapphire substrates or accepting their thermal expansion mismatch issues
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces stress between the epitaxial and substrate layers, enhancing yield and reducing manufacturing costs while allowing for broader application and simpler processing.
Implementation Method 1
the thermal expansion coefficients of the epitaxial layer and the protective layer are both either greater than or less than that of the silicon substrate
Data Source
AI summary
A laminar structure of semiconductors comprises a silicon substrate, an epitaxial layer, a protective layer, a first layer and a second layer. The epitaxial layer is arranged above the silicon substrate and the protective layer is arranged below the silicon substrate. Thermal expansion coefficients of the epitaxial layer and the protective layer are both either greater than or less than that of the silicon substrate. The first layer is arranged between the silicon substrate and the protective layer; and the second layer is arranged between the silicon substrate and the epitaxial layer, wherein the band gap of the first layer and the second layer are both greater than 3 eV. By arranging the protective layer below the silicon substrate, stress generated between the silicon substrate and the epitaxial layer can be reduced to prevent occurrence of bending or crack. Therefore, yield can be promoted and costs can be reduced.