Semiconductor Land Structure for Thermal Stress Relief
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Solution Overview
Problem
Conventional semiconductor devices face disconnection issues due to thermal stress between copper wiring and silicon substrates, leading to increased line resistance, signal attenuation, and reduced integration density, particularly at the edges and root portions of vias and external terminals.
Innovation Solution
A semiconductor device design featuring a seed layer with land portions of varying diameters and shapes, under bump metal layers with tapered edges, and dielectric coverage to alleviate stress through deformation of the wiring pattern, reducing the concentration of thermal expansion differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the wiring pattern is extended to improve stress resistance, then reliability is improved, but line resistance, inductance, and capacitance increase causing signal attenuation and propagation delay
Solution Approach 1:
The patent introduces a three-dimensional land portion structure with varying diameters at different heights. The land portion has a first diameter at a first height and a second diameter at a second height, creating a stepped configuration that distributes stress across multiple dimensions rather than extending the wiring pattern horizontally, thus avoiding increased line resistance and signal loss.
2Reliability
If the wiring pattern is extended to improve stress resistance, then reliability is improved, but wiring space increases reducing integration density
Solution Approach 1:
The patent utilizes vertical dimensionality with land portions having different diameters at different heights to achieve stress resistance. This vertical expansion allows the structure to accommodate thermal stress without requiring additional horizontal wiring space, thereby maintaining high integration density while improving reliability.
Solution Approach 2:
The patent changes the physical parameters of the land portion by varying its diameter at different heights. The first land portion has a first diameter at a first height, while the second land portion has a second diameter at a second height, creating a graduated structure that optimizes stress distribution without increasing the planar footprint, thus preserving integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces stress concentrations at critical areas, enhancing the reliability and integration density of semiconductor devices by allowing the wiring pattern to deform and move with thermal changes, thereby preventing disconnection and signal delays.
Implementation Method 1
the linear expansion coefficient of silicon is 2×10−6 (1/K), the linear expansion coefficient of copper is about 17×10−6 (1/K), which is about 8.5 times as large as that of silicon. For this reason, a thermal expansion difference is generated between silicon and copper due to self-heating of the semiconductor device
Data Source
AI summary
Provided are a semiconductor device having a stress alleviation structure in which resistance to stress concentrated on a predetermined portion of the semiconductor device is improved, and a method for manufacturing the semiconductor device. The semiconductor device includes: a first dielectric layer; a seed layer having a first land portion formed on the first dielectric layer; a second land portion formed on the seed layer and having a diameter larger than a diameter of the first land portion that can be connected to the wiring pattern; an external terminal formed on the second land portion; and a second dielectric layer covering the seed layer, the first land portion, and the second land portion.