Semiconductor Device High-Doped Landing Pad Contact Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing vertical channel memory devices face challenges in achieving small size and large memory capacity due to the use of thin polysilicon as a channel layer, which can lead to contact landing risks and overlap issues during the lithography process.
Innovation Solution
A semiconductor device is designed with a charge trapping structure and a high-doped semiconductor layer to form a thick landing pad, allowing stable connection with a conductive plug, and a manufacturing method that alternately stacks semiconductor and insulating layers, deposits a channel layer, and etches to create a U-shaped structure, eliminating the need for extra lithography and avoiding contact landing risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a thin polysilicon layer is used as the channel layer to reduce device size, then the device dimensions are reduced, but contact landing reliability deteriorates
Solution Approach 1:
The patent segments the polysilicon structure into multiple functional layers: a thin channel layer (50) for small size and a separate thick high-doped landing pad layer (70) for reliable contact. This segmentation allows each layer to optimize for its specific function, resolving the contradiction between small size and contact reliability.
Solution Approach 2:
The patent extends the polysilicon structure vertically by adding the high-doped landing pad layer beneath the channel layer. This dimensional extension provides a large contact area for conductive plugs while maintaining a thin channel layer, thus achieving both small device size and reliable contact landing.
2Reliability
If an extra lithography process is added to form the channel layer, then contact landing reliability is improved, but device complexity increases
Solution Approach 1:
The patent performs preliminary action by forming the high-doped landing pad layer (70) before depositing the channel layer (50). The landing pad layer is prepared in advance with proper doping and thickness, so that when the channel layer is deposited, reliable contact is already established without requiring additional lithography steps.
Solution Approach 2:
The channel layer deposition process automatically forms the contact structure by conformally coating the high-doped landing pad layer. The existing landing pad structure guides the deposition process to create properly aligned contacts, eliminating the need for separate lithography alignment steps.
3Volume of moving object
If the channel layer thickness is reduced to achieve small size, then device dimensions are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The high-doped landing pad layer (70) acts as an intermediary between the substrate and the thin channel layer (50). It provides a robust, thick foundation that compensates for the thinness of the channel layer, reducing the precision requirements for channel layer thickness control while maintaining overall device integrity and contact reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances storage capacity and stability by ensuring reliable contact between layers without the need for additional lithography, thus preventing contact landing risks and overlap issues, enabling a more efficient manufacturing process.
Implementation Method 1
a high-doped semiconductor layer is deposited to form a thick landing pad for stably connecting with a conductive plug
Implementation Method 2
a channel layer are sequentially deposited on surfaces of the stacked structures
Implementation Method 3
Part of the channel layer is removed to expose a top surface of the charge trapping structure. The charge trapping structure on the silicon nitride layer is removed. An etching process is implemented to separate the high-doped semiconductor layer
Data Source
AI summary
A semiconductor device including a substrate, a bottom insulating layer disposed on the substrate, two stacked structure disposed on the bottom insulating layer, a charge trapping structure, and a channel layer disposed on the charge trapping structure is provided. Each of the stacked structures includes a plurality of semiconductor layers and insulating layers, a top insulating layer disposed on the semiconductor layers and the insulating layers, and a high-doped semiconductor layer disposed on the top insulating layer. The semiconductor layers and the insulating layers are alternately stacked on the bottom insulating layer. The charge trapping layer is disposed on a lateral surface of each of the stacked structures and a top surface of the bottom insulating layer. The channel layer is directly contacted the high-doped semiconductor layer.