Semiconductor Landing Pads With Insulating Spacers
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Solution Overview
Problem
As the integration of semiconductor devices increases, design rules for elements become more complex, requiring innovative solutions for efficient contact structures that minimize contact resistance and prevent short circuits between conductive lines.
Innovation Solution
The semiconductor device incorporates a substrate with conductive lines, insulating spacers, and landing pads of different materials, where contact plugs and landing pads are integrally connected, with metal silicide layers between them, and insulating capping lines to enhance contact areas and reduce the likelihood of short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs and landing pads are made with larger contact areas to reduce contact resistance, then contact resistance decreases, but device area increases
Solution Approach 1:
The patent transitions from planar contact structures to three-dimensional stacked structures. Contact plugs extend vertically through multiple insulating layers to reach active regions, and landing pads are stacked in multiple layers (first landing pads, second landing pads, third landing pads) at different heights. This vertical dimensionality allows increased contact area without proportionally increasing the horizontal device footprint, effectively reducing contact resistance while maintaining compact device area.
Solution Approach 2:
The patent implements nested contact structures where contact plugs are positioned within openings of insulating layers, and landing pads are nested within landing pad holes in the insulating patterns. The contact plugs connect to active regions and extend upward, while multiple layers of landing pads are nested around and along the contact plugs at different vertical levels. This nesting arrangement maximizes contact area utilization within the available vertical space.
2Productivity
If conductive lines are placed closer together to increase integration density, then device integration increases, but risk of short circuits between conductive lines increases
Solution Approach 1:
The patent introduces multiple insulating layers (first insulating layer, second insulating layer, third insulating layer) as intermediary materials between conductive lines and between contact structures. These insulating layers act as mediators that electrically isolate adjacent conductive lines and prevent short circuits. The insulating patterns with landing pad holes provide controlled pathways for electrical connection while maintaining isolation in other regions, enabling high integration density with reliable short circuit prevention.
Solution Approach 2:
The patent segments the conductive interconnect structure into multiple discrete layers and components. Conductive lines are separated by insulating layers, and contact structures are divided into distinct segments (contact plugs, first landing pads, second landing pads, third landing pads) at different vertical levels. This segmentation allows conductive elements to be placed closer together in the horizontal plane while maintaining electrical isolation through the vertical stacking of insulating and conductive layers.
3Reliability
If contact plugs extend deeper into the substrate to reach active regions, then electrical connection reliability improves, but manufacturing complexity increases
Solution Approach 1:
The patent forms insulating layers and insulating patterns with predetermined thicknesses and structures before forming the contact plugs. The first insulating layer, second insulating layer, and third insulating layer are deposited and patterned in advance, creating a prepared substrate structure with defined openings and landing pad holes. This preliminary preparation establishes clear pathways and depth requirements for contact plug formation, simplifying the subsequent contact formation process while ensuring reliable electrical connections to active regions.
Data Source
AI summary
A semiconductor device including a substrate, the substrate including active regions; a pair of conductive lines spaced apart from the substrate such that an insulating layer is between the substrate and the pair of conductive lines; insulating spacers covering side walls of each of the pair of conductive lines such that contact holes having first widths in a first direction are defined between the pair of conductive lines; upper insulating patterns on the pair of conductive lines, the upper insulating patterns defining landing pad holes connected to the contact holes such that the landing pad holes have second widths in the first direction that are greater than the first widths; contact structures including contact plugs connected to the active regions by passing through the insulating layer, and first landing pads connected to the contact plugs, the first landing pads being in the landing pads holes such that the first landing pads vertically overlap with one of the pair of conductive lines; and capacitor lower electrodes connected to the contact structures.