Semiconductor Die Embedding With Laser-Structured Conductive Passageways
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Solution Overview
Problem
Current semiconductor device manufacturing, particularly for QFN packages, faces limitations in reducing wiring, enhancing current distribution flexibility, integrating passive components, improving transistor performance, and reducing mechanical stress, while also dealing with the unavailability of the top surface of the semiconductor die for connection and the complexity of wire bonding layouts.
Innovation Solution
The implementation of electrically-conductive passageways and lines within the packaging material, created using laser direct structuring technology, which allows for the elimination of wire bonding and the integration of passive components, while maintaining flexibility in signal and current distribution, and reducing mechanical stress by providing alternative pathways for electrical connections and thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to provide electrical connections in QFN packages, then electrical connectivity is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts the wire bonding step from the manufacturing process by providing pre-formed electrical connection means (leads or trace patterns) on the support substrate that directly connect to the semiconductor die, eliminating the need for separate wire bonding operations and reducing layout complexity
Solution Approach 2:
The electrical connection means are prepared in advance on the support substrate with predetermined connection patterns, allowing direct attachment of the semiconductor die without requiring complex wire bonding layouts to be designed and executed during assembly
2Adaptability or versatility
If the top surface of the semiconductor die is used for connections, then connection options are limited, but using alternative approaches increases manufacturing flexibility
Solution Approach 1:
The patent moves electrical connections from the traditional top-surface approach to alternative dimensions by providing connection means on the support substrate that connect to the bottom surface or side surfaces of the semiconductor die, enabling greater flexibility in connection routing and passive component integration
Solution Approach 2:
The support substrate is divided into functional regions including electrical connection means, passive component mounting areas, and thermal dissipation zones, allowing independent optimization of each function without interfering with the others
3Adaptability or versatility
If wiring is reduced in QFN packages, then current distribution flexibility improves, but alternative current pathways must be provided
Solution Approach 1:
The support substrate serves multiple functions simultaneously: it provides mechanical support, electrical connections through integrated leads or traces, passive component mounting, and thermal management, eliminating the need for separate wiring layers and simplifying current distribution pathways
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of semiconductor devices by reducing mechanical stress, improving current distribution, and allowing for the integration of passive components within the package, thereby improving the overall efficiency and flexibility of semiconductor device manufacturing.
Implementation Method 1
created using laser direct structuring technology
Data Source
AI summary
A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate.