Semiconductor Fabrication Using Laser Crystallization for Sub-50 nm Isolation
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Solution Overview
Problem
Conventional methods find it difficult to fabricate semiconductor devices with isolation layers less than 50 nm width and channel regions comprising single-crystalline silicon and single-crystalline silicon-germanium, which are required for advanced CMOS transistors and silicon-on-insulator substrates.
Innovation Solution
A method involving the formation of insulation layer structures with etch selectivities, followed by selective etching and laser irradiation to create single-crystalline silicon and silicon-germanium patterns, allowing for the fabrication of semiconductor devices with narrow isolation layers and high-quality channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used, then manufacturing process is simple, but isolation layer width cannot be reduced below 50 nm
Solution Approach 1:
The fabrication process is divided into multiple sequential stages: forming the insulation layer structure with multiple layers, selective etching to create first and second openings, filling with different materials (silicon for first opening, silicon-germanium for second opening), and separate laser irradiation treatments. This segmentation enables precise control of the isolation layer width below 50 nm while maintaining manufacturing feasibility through systematic process breakdown
Solution Approach 2:
The insulation layer structure is formed in advance with multiple layers having different etch selectivities before the actual pattern formation. This preliminary structuring allows subsequent selective etching to precisely define the isolation layer boundaries at sub-50 nm dimensions, achieving high precision without requiring complex real-time control during etching
2Reliability
If single-crystalline silicon and single-crystalline silicon-germanium channel regions are formed using conventional methods, then electrical performance is improved, but fabrication difficulty increases
Solution Approach 1:
Different channel regions are formed with distinct material properties: the first channel region uses single-crystalline silicon while the second channel region uses single-crystalline silicon-germanium. Each region receives tailored laser irradiation treatment to achieve the desired crystal structure. This local differentiation enables optimized electrical performance for each transistor type while managing fabrication complexity through targeted processing
Solution Approach 2:
Conventional mechanical or thermal crystallization methods are replaced with laser beam irradiation to form single-crystalline structures. The laser provides localized energy delivery that transforms the material into single-crystalline form without requiring complex mechanical pressing or extended thermal processing, thereby reducing fabrication difficulty while maintaining high electrical performance
3Productivity
If isolation layer width is reduced to less than 50 nm, then device density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The isolation layer width control is achieved by transitioning from direct lateral patterning to vertical layering followed by selective removal. Multiple insulation layers are deposited vertically with different etch selectivities, then selectively etched away to reveal the isolation layer. This dimensional approach to patterning enables sub-50 nm precision by using the vertical dimension for process control rather than relying solely on lateral lithographic resolution
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the fabrication of semiconductor devices with isolation layers less than 50 nm wide and channel regions of single-crystalline silicon and silicon-germanium, improving electrical performance and manufacturing reliability.
Implementation Method 1
forming a single-crystalline silicon pattern by irradiating the non-single-crystalline silicon layer with a first laser beam
Implementation Method 2
forming a single-crystalline silicon-germanium pattern by irradiating the non-single-crystalline silicon-germanium layer with a second laser beam
Implementation Method 3
forming a first insulation layer structure pattern by etching a portion of the insulation layer structure
Data Source
AI summary
A method of fabricating a semiconductor device includes forming an insulation layer structure on a single-crystalline silicon substrate, forming a first insulation layer structure pattern comprising a first opening by etching a portion of the insulation layer structure, filling the first opening with a non-single-crystalline silicon layer, and forming a single-crystalline silicon pattern by irradiating a first laser beam onto the non-single-crystalline silicon layer. The method also includes forming a second insulation layer structure pattern comprising a second opening by etching a portion of the first insulation layer structure, filling the second opening with a non-single-crystalline silicon-germanium layer, and forming a single-crystalline silicon-germanium pattern by irradiating a second laser beam onto the non-single-crystalline silicon-germanium layer.