Semiconductor Laser Marking and Copper Film Peeling Prevention
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Solution Overview
Problem
The peeling of copper films during the planarization process in semiconductor device manufacturing is caused by the mismatched intervals between wafer edge exclusion, edge bead removal, and laser marking in trench photo etch processes, leading to defects and contamination.
Innovation Solution
A method is introduced to form a laser marking within a specific width from the edge of the wafer, followed by forming trench patterns and a metal interconnection layer, and then removing a predetermined portion of the layer using an edge bead removal process, ensuring the intervals between these processes are adjusted to prevent peeling, specifically by setting the first width of the laser marking and the second width of the edge bead removal to be equal, thereby minimizing the step between the protrusion and trench patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the laser marking depth is increased to identify each metal layer in highly integrated semiconductor devices, then the marking visibility is improved, but the protrusion height increases causing copper film peeling during planarization
Solution Approach 1:
The patent changes the parameter of laser marking depth to optimize the balance between visibility and protrusion height. By controlling the depth D of the laser marking within specific limits, the marking remains visible for identifying metal layers while the protrusion height H is kept minimal to prevent copper film peeling during subsequent planarization processes
Solution Approach 2:
The patent applies partial action by forming the laser marking only to the necessary depth required for identification, rather than excessive depth. This controlled partial marking achieves the identification function while minimizing the protrusion that would otherwise cause adhesion problems with the copper interconnection layer
2Stability of the object's composition
If the trench WEE is set greater than EBR to prevent unfilled trench pattern collapse, then the structural stability is improved, but a Cu belt forms in the interval region causing step increase and copper film peeling
Solution Approach 1:
The patent applies local quality by creating a Cu belt in the specific interval region between trench WEE and EBR. This localized copper formation provides structural support to prevent trench pattern collapse while the belt is strategically positioned to minimize its impact on overall surface flatness and copper film adhesion
Solution Approach 2:
The patent addresses the trench stability problem by transitioning from a two-dimensional trench cross-section to a three-dimensional Cu belt structure. The Cu belt adds vertical dimension support to the trench region, preventing collapse during planarization while the patent simultaneously controls its horizontal positioning to minimize surface step issues
3Strength
If the protrusion height is reduced to prevent copper film peeling, then the copper film adhesion is improved, but the laser marking visibility for identifying metal layers is reduced
Solution Approach 1:
The patent optimizes the parameter relationship between marking depth D and protrusion height H. By establishing specific parameter ranges where the depth is controlled relative to the protrusion height, the laser marking maintains sufficient visibility for metal layer identification while keeping the protrusion minimal to ensure copper film adhesion is not compromised
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents the peeling of the copper film by ensuring the copper film is securely attached to the wafer, reducing defects and contamination, and maintaining the integrity of the semiconductor device during the planarization process.
Implementation Method 1
When a laser is used to form the laser marking 20, a protrusion 22 is formed as a by-product
Implementation Method 2
a predetermined edge portion of the wafer 10 is removed using chemicals
Data Source
AI summary
A method for manufacturing a semiconductor device comprises forming a laser marking, forming a trench pattern, forming a metal interconnection layer, removing a predetermined portion of the metal interconnection layer, and planarizing the metal interconnection layer. The laser marking is formed in a first region of a wafer, and the first region has a first width from an edge of the wafer. The trench pattern is formed above the wafer except for above the first region. The metal interconnection layer is formed above the wafer where the laser marking and the trench pattern are formed. The predetermined portion of the metal interconnection layer is removed, and the predetermined portion has a second width from the edge of the wafer equal to or greater than the first width. And the metal interconnection layer above the wafer where the trench pattern is formed is planarized to a predetermined thickness.