Semiconductor Device Latch Circuit Error Masking
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Solution Overview
Problem
The existing CRC function in DDR4 DRAMs requires time for error detection, leading to a delay in writing data, which can be addressed by inserting multiple latch circuit stages, but this occupies a large chip area.
Innovation Solution
A semiconductor device with a verification circuit that sets an error signal, a latch circuit that latches a data mask signal, and a buffer circuit that outputs the data mask signal, where the first timing signal is activated before the error signal, allowing for error detection without additional latch circuits between the latch and buffer circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple latch circuit stages are inserted in the data bus to delay write data for CRC verification, then the CRC error detection function can be implemented, but a large chip area is occupied by the multiple latch circuits
Solution Approach 1:
The invention extracts the verification function from the data path by moving it to the data mask signal path. Instead of delaying write data through multiple latch circuits, the verification circuit processes write data separately and controls the data mask signal to block erroneous data, thereby eliminating the need for multiple latch circuits in the data bus.
Solution Approach 2:
The invention introduces a data mask signal as an intermediary to control data flow. The latch circuit latches the data mask signal instead of latching write data itself, and this latched mask signal then controls whether write data is written to memory. This intermediary approach allows verification without requiring multiple data latch stages.
2Reliability
If write data is delayed to allow CRC calculation completion, then error detection can be performed before writing, but writing speed is reduced
Solution Approach 1:
The verification circuit performs CRC calculation on write data in advance before the data mask signal is latched. By completing verification beforehand and using the result to control the data mask signal timing, the system ensures error detection without requiring delay of the actual write data transmission to memory.
Solution Approach 2:
The invention maintains continuous data flow by separating verification from data transmission. Write data continuously flows to memory while verification occurs in parallel on copied data. The data mask signal acts as a gate that only blocks data when errors are detected, otherwise allowing uninterrupted writing.
Data Source
AI summary
Embodiments of the present invention relate to a latch circuit (L20) which latches a data mask signal (DM) in response to a one-shot signal (NS), and changes the data mask signal (DM) to an active level in response to an error signal (ERR), which indicates that an error is present in write data (DQ), being at an active level; a buffer circuit (BF2) which outputs the data mask signal (DM) that has been latched by the latch circuit (L20), said data mask signal (DM) being output in response to a write clock signal (WCLK2); and a main amplifier (80) which outputs the write data (DQ) to an internal circuit on the condition that the data mask signal (DM) which has been output from the buffer circuit (BF2) is at an inactive level. The present invention can prevent the writing of erroneous write data, and is capable of preventing increased chip surface area.