Semiconductor Latch Circuit Noise Cancellation
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Solution Overview
Problem
Conventional semiconductor devices with PMOS transistors disposed in a single N well have low soft error resistance due to two nodes with the same data being close and simultaneously exposed to noise, leading to inverted latch circuit states.
Innovation Solution
A semiconductor device with a latch circuit configuration where four inverting circuits are arranged such that the distance between drain nodes with different data is shorter than those with the same data, enhancing noise cancellation and soft error resistance, while also allowing for a smaller area by disposing drain nodes in specific well regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If PMOS transistors are disposed in a single N well to reduce area, then area is reduced, but two nodes with the same data are disposed close to each other and are readily and simultaneously exposed to noise, reducing soft error resistance
Solution Approach 1:
The latch circuit is segmented into four separate inverting circuits instead of using a conventional two-inverter configuration. Each inverting circuit has its own distinct drain nodes, which are strategically positioned to be spatially separated. This segmentation allows the circuit to maintain compact area while ensuring that nodes with the same data are not disposed close to each other, thereby preventing simultaneous noise exposure and maintaining soft error resistance.
Solution Approach 2:
Different spatial arrangements are applied to different parts of the latch circuit. Specifically, drain nodes with the same data (e.g., drain nodes of first and third inverting circuits, and drain nodes of second and fourth inverting circuits) are disposed at greater distances from each other compared to drain nodes with different data. This local quality differentiation ensures that noise affecting one node is less likely to simultaneously affect another node with the same data, thereby improving soft error resistance without significantly increasing overall area.
2Reliability
If PMOS and NMOS transistors are alternately disposed to cancel noise, then soft error resistance is improved, but disposition efficiency deteriorates and area cannot be decreased
Solution Approach 1:
The latch circuit uses an asymmetric configuration of four inverting circuits with unequal spacing arrangements. The drain nodes are not uniformly distributed but are specifically positioned such that nodes with the same data are farther apart than nodes with different data. This asymmetric disposition achieves noise cancellation and soft error resistance without requiring the alternating PMOS-NMOS pattern, thereby improving disposition efficiency and reducing area.
3Reliability
If distance between drain nodes with different data is made shorter than distance between drain nodes with same data, then noise cancellation is enhanced, but device complexity increases
Solution Approach 1:
The latch circuit merges the functionality of multiple inverting circuits into a unified four-inverter configuration where the drain nodes of all inverting circuits are disposed in the same N well region. This merging approach simplifies the overall device structure by consolidating components into a compact arrangement while maintaining the asymmetric spacing of drain nodes. The unified configuration reduces device complexity compared to separate dispersed inverting circuits, while still achieving enhanced noise cancellation through the strategic positioning of drain nodes.
Data Source
AI summary
A semiconductor device includes: a first latch circuit that includes a first inverting circuit, a second inverting circuit, a third inverting circuit, and a fourth inverting circuit; a first first-type well region; a second first-type well region; and a second-type well region. In a plan view, a distance between a drain of a first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the third inverting circuit is longer than a distance between the drain of the first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the fourth inverting circuit.