Semiconductor Device Latency Measurement Sampling

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Solution Overview

Problem

Current semiconductor devices face challenges in efficiently measuring latency in channels between master and slave devices within System-on-Chip (SoC) due to resource-intensive latency counting for multiple transactions, which consumes significant resources and complicates debugging and Quality-of-Service (QoS) control.

Innovation Solution

The proposed solution involves a semiconductor device with a monitoring system that uses a configuration module to filter target request packets based on predefined ID information, a latency counter to measure latency, and a control module to detect response packets, allowing for efficient measurement of latency in specific transactions using a sampling technique, thereby minimizing resource usage while maintaining precision.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If latency counting is performed for multiple transactions simultaneously, then comprehensive latency measurement is achieved, but resource consumption increases significantly

Engineering Contradiction:
Improvelatency measurement comprehensivenessVSAvoidresource consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent implements sampling-based latency measurement where only selected transactions are measured instead of all transactions. The latency counter is activated selectively based on sampling criteria, measuring latency for a subset of transactions that represents the overall behavior. This partial measurement approach reduces resource consumption while maintaining measurement effectiveness through statistical representation.

Inventive Principle:
Principle #16Partial or excessive action

2Measurement precision

If latency measurement is performed for all transactions, then complete latency data is obtained, but device complexity increases

Engineering Contradiction:
Improvelatency data completenessVSAvoidmeasurement system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The system uses sampling to select a representative subset of transactions for latency measurement. The control logic activates the latency counter only for selected transactions based on sampling criteria, avoiding the complexity of tracking and measuring every single transaction. This reduces the complexity of the measurement system while obtaining sufficient latency data through statistical sampling.

Inventive Principle:
Principle #16Partial or excessive action

3Use of energy by moving object

If sampling technique is used for latency measurement, then resource consumption is reduced, but measurement precision may be compromised

Engineering Contradiction:
Improveresource consumptionVSAvoidlatency measurement accuracy
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The sampling-based latency measurement system incorporates feedback mechanisms where measurement results from sampled transactions are used to validate and adjust the sampling strategy. The system monitors the representativeness of sampled data and can adapt sampling criteria to ensure measurement precision is maintained despite measuring only a subset of transactions. This feedback loop ensures that resource-efficient sampling does not compromise the accuracy of latency measurements.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10564855B2Semiconductor device and operating method thereof
Publication Date: 2020.02.18 SAMSUNG ELECTRONICS CO LTD
  • US10564855B2 patent drawing
  • US10564855B2 patent drawing
  • US10564855B2 patent drawing

AI summary

An operating method of a semiconductor device includes monitoring multiple request packets and multiple response packets that are being transmitted between a master device and a slave device. A target request packet that matches predefined identification (ID) information is detected from among the request packets. An operation of a latency counter is initiated. The operation is for measuring the latency of a communication exchange (transaction) that includes the target request packet and a target response packet that is one of the response packets that matches the predefined ID information. The target response packet is detected from among the response packets. The operation of the latency counter is terminated. A latency value of the communication exchange is acquired from the latency counter.