Semiconductor Device Minority Carrier Lifetime Control
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices with a pn junction, such as IGBTs, face challenges in precisely controlling the lifetime of minority carriers due to the recovery of lattice defects during the annealing process, making it difficult to achieve high-speed switching.
Innovation Solution
A method involving the formation of a lattice defect layer in a substrate by injecting charged particles and subsequent laser annealing to selectively activate a laminated region, allowing for precise control of the minority carrier lifetime without recovering lattice defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a heat processing furnace is used for annealing after lattice defect layer formation, then the laminated region can be activated, but the lattice defect layer recovers (becomes extinct) making it difficult to control minority carrier lifetime
Solution Approach 1:
The patent divides the thermal processing into two distinct stages: first forming the lattice defect layer by charged particle irradiation, then separately activating the laminated region through laser annealing. This segmentation prevents the lattice defects from recovering while still achieving impurity activation, resolving the contradiction between maintaining lattice defects and activating the laminated region.
Solution Approach 2:
The patent replaces the conventional heat processing furnace (thermal field) with laser annealing (optical field) for activating the laminated region. This substitution allows for localized, controlled heating that activates the laminated region without providing sufficient thermal energy and time for lattice defect recovery, thus maintaining lattice defect stability while achieving activation.
2Manufacturing precision
If conventional heat processing furnace annealing is applied, then the laminated region can be activated, but temperature and time conditions cannot be precisely adjusted leading to lattice defect recovery
Solution Approach 1:
The patent replaces conventional furnace annealing with laser annealing technology. The laser system provides precise control over heating parameters (power, duration, spot size) enabling activation of the laminated region without excessive thermal exposure that would cause lattice defect recovery. This achieves high manufacturing precision with manageable process control.
Solution Approach 2:
The patent changes the thermal processing parameters by using laser annealing with specific power density and duration settings that are optimized to activate the laminated region while keeping the total thermal exposure below the threshold for lattice defect recovery. This parameter optimization achieves precise control over the activation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacturing of semiconductor devices with improved control over minority carrier lifetime, facilitating high-speed switching by maintaining the resistivity of the lattice defect layer and avoiding the recovery of lattice defects, thus enhancing switching performance.
Implementation Method 1
forming a lattice defect layer in a substrate having a front surface region where the bipolar element is formed and a rear surface region opposing the front surface region, the lattice defect layer being formed by injecting a charged particle to a first region in the rear surface region of the substrate
Implementation Method 2
selectively activating the laminated region by laser annealing after the formation of the laminated region and the lattice defect layer
Data Source
AI summary
A method of manufacturing a semiconductor device includes: forming a lattice defect layer in a substrate having a front surface region where a bipolar element of a pn junction type is formed and a rear surface region opposing the front surface region, the lattice defect layer being formed by injecting a charged particle to a first region in the rear surface region of the substrate; forming a laminated region, in which a first conductivity type impurity region and a second conductivity type impurity region are sequentially laminated from a rear surface side of the substrate toward the first region, in a second region in the rear surface region of the substrate, the first region being positioned deeper than the second region from a rear surface of the substrate; and selectively activating the laminated region by laser annealing after the formation of the laminated region and the lattice defect layer.