III-V Semiconductor Layered Structure Lattice Mismatch Control
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Solution Overview
Problem
The production of semiconductor devices using large-diameter substrates is hindered by a high probability of substrate cracking, leading to reduced yield and increased production costs, which hampers the cost reduction goal for III-V compound semiconductor devices.
Innovation Solution
A semiconductor layered structure and method that include a substrate with a diameter of 55 mm or more, featuring a buffer layer and a quantum well layer with specific lattice constant mismatches between the substrate, buffer, and quantum well layers, adjusted to within ±3×10−3, to minimize warping and cracking during production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large-diameter substrates (more than 2 inches) are used to efficiently produce semiconductor devices, then productivity and cost reduction are improved, but the probability of substrate cracking increases, leading to reduced yield
Solution Approach 1:
The patent applies parameter changes by precisely controlling the lattice constant mismatch between the substrate and buffer layer, and between the substrate and quantum well layer. By adjusting the composition ratios of III-V compound semiconductors to maintain lattice constant differences within ±3×10−3, the internal stress in the layered structure is minimized, thereby preventing substrate cracking while enabling the use of large-diameter substrates for high-productivity device fabrication
Solution Approach 2:
The patent employs composite materials by creating a multi-layer structure consisting of a substrate, buffer layer, and quantum well layer, each made of specifically composed III-V compound semiconductors. This composite structure allows optimization of each layer's composition to achieve lattice constant matching, reducing overall structural stress and preventing cracking in large-diameter substrates during device production
2Ease of manufacture
If large-diameter substrates are used to reduce production cost, then cost efficiency is improved, but manufacturing precision deteriorates due to increased cracking probability
Solution Approach 1:
The patent applies parameter changes by precisely controlling the lattice constant mismatch between the substrate and buffer layer, and between the substrate and quantum well layer. By adjusting the composition ratios of III-V compound semiconductors to maintain lattice constant differences within ±3×10−3, the internal stress in the layered structure is minimized, thereby preventing substrate cracking while enabling the use of large-diameter substrates for high-productivity device fabrication
Solution Approach 2:
The buffer layer serves as an intermediary between the substrate and the quantum well layer, accommodating lattice constant differences and reducing stress transmission. This intermediary layer prevents cracking from propagating through the structure, maintaining manufacturing precision while using cost-effective large-diameter substrates
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses cracking in the production process, thereby increasing the yield of semiconductor devices and enabling efficient production using larger substrates, such as those with diameters up to 6 inches, while maintaining high crystallinity and sensitivity for infrared photodiodes.
Implementation Method 1
a buffer layer disposed on and in contact with the substrate and formed of a III-V compound semiconductor, and a quantum well layer disposed on and in contact with the buffer layer
Data Source
AI summary
A semiconductor layered structure includes a substrate formed of a III-V compound semiconductor, a buffer layer disposed on and in contact with the substrate and formed of a III-V compound semiconductor, and a quantum well layer disposed on and in contact with the buffer layer and including a plurality of component layers formed of III-V compound semiconductors. The substrate has a diameter of 55 mm or more. At least one of the component layers is formed of a mixed crystal of three or more elements. When the compound semiconductor forming the substrate has a lattice constant d1, the compound semiconductor forming the buffer layer has a lattice constant d2, and the compound semiconductors forming the quantum well layer have an average lattice constant d3, (d2−d1)/d1 is −3×10−3 or more and 3×10−3 or less, and (d3−d1)/d1 is −3×10−3 or more and 3×10−3 or less.