Semiconductor Structure with Lattice-Mismatched Layer for Spike Control
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Solution Overview
Problem
The interface between aluminium metal layers and semiconductor substrates is prone to the formation of deep spikes during annealing, which can cause current filaments and short circuits in semiconductor devices, and existing methods to mitigate this, such as lowering annealing temperatures or using barrier layers, are limited in effectiveness.
Innovation Solution
A semiconductor structure is created with a first monocrystalline semiconductor portion and a second monocrystalline semiconductor portion of different lattice constants, with the second portion forming a layer between the substrate and the metal layer, allowing for controlled spike formation and reduced depth of spikes during annealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier layer is formed between the semiconductor substrate and metal layer to prevent spike formation, then spike generation is reduced, but the barrier layer may enhance spike generation if defective and affects contact resistance
Solution Approach 1:
The patent changes the crystallographic orientation parameter of the semiconductor substrate surface from conventional <100> to <110>. This parameter change fundamentally alters the interface properties between semiconductor and metal, preventing spike formation without requiring additional barrier layers, thus maintaining good ohmic contact resistance while eliminating the reliability risks associated with defective barrier layers
Solution Approach 2:
The patent uses the crystallographic orientation of the semiconductor substrate surface as an intermediary mechanism to prevent spike formation. The specific <110> orientation acts as a natural barrier to aluminium penetration into the substrate, replacing the need for artificial barrier layers and directly controlling the metal-semiconductor interface behavior
2Reliability
If annealing temperature is lowered to reduce spike formation, then spike depth is reduced, but this approach is only possible in limited cases
Solution Approach 1:
The patent changes the crystallographic orientation parameter from <100> to <110>, which fundamentally alters the spike formation mechanism. This allows annealing to be performed at conventional temperatures (350-450°C) while still preventing deep spike formation, thereby maintaining process flexibility and adaptability across different manufacturing scenarios
3Reliability
If aluminium metal layer is used for its low ohmic resistance and good contact properties, then electrical performance is improved, but deep spikes form during annealing causing current filaments and short circuits
Solution Approach 1:
The patent changes the surface orientation parameter of the semiconductor substrate to <110>, which fundamentally alters the interaction between aluminium and the semiconductor lattice during annealing. This parameter change maintains the low ohmic resistance and good contact properties of aluminium while preventing the formation of harmful deep spikes that cause current filaments and short circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a more uniform and shallower spike formation, reducing the risk of current filaments and short circuits, while maintaining good contact resistance and allowing for the formation of pn-junctions and buried doping regions at a lower depth, thus enhancing the reliability of semiconductor devices.
Implementation Method 1
Spikes form during annealing which is typically carried out after deposition of the aluminium metal layer, for example in a temperature range between 350° C. and 450° C.
Data Source
AI summary
According to an embodiment, a semiconductor structure includes a first monocrystalline semiconductor portion having a first lattice constant in a reference direction; a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion; and a metal layer formed on and in contact with the second monocrystalline semiconductor portion.