Semiconductor Layer Calibration Standards for S-Parameter Testing
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Solution Overview
Problem
Existing testing instruments face challenges in calibrating S-parameters of devices-under-test, particularly when the reference plane is located at the electrical access layer of a package, limiting direct comparability with circuit simulations and package defect detection, and requiring matching structures for non-standard impedances, which can introduce inaccuracies and damage risks.
Innovation Solution
Integrating calibration standards at the semiconductor layer of integrated circuits within a compound, allowing the reference plane to be shifted to a location not physically accessible by the testing instrument, enabling calibration without matching structures and accommodating arbitrary impedances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If calibration standards are integrated at the electrical access layer of a package, then the reference plane can be accessed by the testing instrument, but measurement accuracy is limited and direct comparability with circuit simulations is lost
Solution Approach 1:
The patent integrates calibration standards at the semiconductor layer (a lower dimensional plane within the package) rather than at the electrical access layer surface. This dimensional shift allows the reference plane to be positioned at the semiconductor layer where calibration standards are integrated, enabling both accurate measurements and direct comparability with circuit simulations while maintaining accessibility through the package structure.
2Adaptability or versatility
If matching structures are used for non-standard impedances, then the testing instrument can be calibrated, but inaccuracies are introduced and damage risks increase
Solution Approach 1:
The patent integrates calibration standards with arbitrary impedance values directly at the semiconductor layer, eliminating the need for matching structures. By changing the impedance parameter of the calibration standards to match the arbitrary impedance requirements, the system achieves both adaptability to non-standard impedances and maintains measurement accuracy without introducing inaccuracies or damage risks.
3Ease of operation
If the reference plane is located at the electrical access layer, then the testing instrument can perform measurements, but direct comparability with circuit simulations and package defect detection are limited
Solution Approach 1:
The patent performs calibration at the semiconductor layer (a preliminary stage within the package structure) by integrating calibration standards at this lower layer. This preliminary calibration action establishes the reference plane at the semiconductor layer, enabling both measurement capability and direct comparability with circuit simulations and package defect detection to be achieved simultaneously.
Data Source
AI summary
A compound may include a set of integrated circuits. An integrated circuit, of the set of integrated circuits, may include calibration standards integrated at a silicon layer of the integrated circuit. The integrated circuit may be included in a package, and a calibration standard, of the calibration standards, may be available to at least one port of a set of ports of the integrated circuit.