3D Nonvolatile Memory Semiconductor Layer Curvature Control
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Solution Overview
Problem
The manufacturing method of three-dimensional nonvolatile semiconductor memory devices results in a concave curve on the side surface of the semiconductor layer, leading to electric field concentration and characteristic deterioration of the memory cell due to the tapered portion formed between the oxide layers, making it difficult to achieve high integration and capacity.
Innovation Solution
A new oxide layer is formed on the surface of the semiconductor layer to reduce the curvature of the concave curve, preventing electric field concentration by diffusing oxygen from the existing oxide layers to the semiconductor layer through a heat treatment process, thereby improving the memory cell's characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If wet etching is used to recess the side surface of the semiconductor layer, then the width of the semiconductor layer is reduced, but a concave curve is formed on the side surface leading to electric field concentration
Solution Approach 1:
The patent applies parameter changes by modifying the etching conditions (etchant concentration, temperature, time) to control the etching rate and minimize concave curve formation. It also changes the surface treatment parameters by forming an oxide layer with specific thickness and performing controlled thermal oxidation to reshape the surface profile.
Solution Approach 2:
The patent replaces the mechanical/chemical etching process that creates concave curves with a thermal oxidation process. By substituting the etching mechanism with thermal field action, the surface is reshaped through controlled oxidation that fills in the concave regions and creates a more uniform surface profile.
2Productivity
If the semiconductor layer is recessed to shrink its width, then integration density is improved, but a tapered portion is formed that causes electric field concentration and characteristic deterioration
Solution Approach 1:
The patent converts the harmful tapered portion and concave curve into a benefit by using controlled thermal oxidation. The oxidation process selectively modifies the surface profile, transforming the problematic geometry into a beneficial shape that eliminates electric field concentration while maintaining the reduced width for high integration density.
Solution Approach 2:
The patent applies local quality by performing selective surface treatment on specific regions. The thermal oxidation is applied locally to the recessed areas with different kinetics, creating a graded surface profile that eliminates the tapered portion at critical locations while preserving the overall shrunk dimensions for high integration.
3Manufacturing precision
If a new oxide layer is formed through heat treatment, then the curvature of the concave curve is reduced, but additional manufacturing steps are required
Solution Approach 1:
The patent merges multiple functions into a single thermal oxidation step. The same heat treatment process simultaneously forms the new oxide layer, reshapes the concave curve surface, and prepares the surface for subsequent processing. This consolidation reduces the total number of discrete manufacturing steps while achieving multiple objectives.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new oxide layer reduces the curvature of the semiconductor layer's concave curve, preventing electric field concentration and enhancing the memory cell's performance and reliability, allowing for improved integration and capacity in three-dimensional nonvolatile semiconductor memory devices.
Implementation Method 1
diffusing oxygen from the existing oxide layers to the semiconductor layer through a heat treatment process
Implementation Method 2
through a heat treatment process
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes a fin structure stacked in order of a first oxide layer, a semiconductor layer and a second oxide layer in a first direction perpendicular to a surface of the semiconductor substrate, the fin structure extending in a second direction parallel to the surface of the semiconductor substrate, and a gate structure stacked in order of a gate oxide layer, a charge storage layer, a block insulating layer and a control gate electrode in a third direction perpendicular to the first and second directions from a surface of the semiconductor layer in the third direction.


