Local Stress in Semiconductor Layers via Insulator Viscosity Control
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Solution Overview
Problem
Existing transistor processing methods result in non-optimal stress in semiconductor layers, leading to suboptimal performance of transistors, as they fail to consistently apply compressive or tensile stress in the channel region effectively.
Innovation Solution
A method involving the deposition of a stress layer over a semiconductor on insulator structure, forming openings aligned with transistor channels, and annealing the insulating layer to decrease its viscosity, thereby locally deforming and maintaining stress in the semiconductor layer, which is then used to form transistor gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing transistor processing methods are used, then manufacturing simplicity is maintained, but stress distribution in the semiconductor layer becomes non-optimal, leading to suboptimal transistor performance
Solution Approach 1:
The patent divides the stress layer into multiple segments by forming openings (trenches) through it. These openings are positioned over specific regions of the semiconductor layer where transistor channels will be formed. This segmentation allows stress to be applied locally and optimally to different channel regions, improving transistor performance while maintaining a relatively simple overall process flow.
Solution Approach 2:
The patent applies different stress conditions to different regions of the semiconductor layer by creating openings in the stress layer only over the channel regions. This local modification ensures that stress is concentrated where it is most needed (in the channel regions) while other regions maintain their original stress state, thereby optimizing transistor performance without unnecessarily complicating the entire device structure.
2Reliability
If stress is applied uniformly across the semiconductor layer, then manufacturing is simpler, but stress concentration in channel regions is insufficient, resulting in non-optimal charge carrier mobility
Solution Approach 1:
The stress layer is segmented by forming openings through it using photolithography and etching processes. These openings are precisely positioned over the channel regions of future transistors. This segmentation enables stress to be concentrated in the channel regions where it is needed to improve charge carrier mobility, while avoiding stress in other regions, thus achieving both high mobility and controlled stress distribution.
Solution Approach 2:
The patent changes the physical and chemical parameters of the insulator layer by annealing it at elevated temperatures (e.g., 950-1150°C). This annealing process modifies the viscosity and mechanical properties of the insulator layer, enabling it to deform and maintain stress in the semiconductor layer. This parameter change allows precise control over stress distribution to optimize charge carrier mobility in channel regions.
3Ease of manufacture
If the insulator layer viscosity is decreased through annealing, then stress deformation capability is improved, but process temperature and time requirements increase
Solution Approach 1:
The patent deliberately changes the temperature parameter by annealing the insulator layer at high temperatures (950-1150°C) to decrease its viscosity. This temporary viscosity reduction enables the insulator layer to deform and maintain stress in the semiconductor layer effectively. The high temperature is applied only for the duration of the annealing process, after which the insulator layer cools and maintains the stress configuration, thus achieving ease of manufacture with controlled temperature application.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the precise and effective introduction of stress in semiconductor layers, enhancing charge carrier mobility and improving transistor performance by maintaining concentrated stress in the channel regions.
Implementation Method 1
deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer
Implementation Method 2
temporally decreasing the viscosity of the insulator layer comprises annealing for a duration of 30 minutes or less
Data Source
AI summary
The disclosure concerns a method of stressing a semiconductor layer comprising: depositing, over a semiconductor on insulator (SOI) structure having a semiconductor layer in contact with an insulating layer, a stress layer; locally stressing said semiconductor layer by forming one or more openings in said stress layer, said openings being aligned with first regions of said semiconductor layer in which transistor channels are to be formed; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.