Semiconductor Layout Structure for High-Density Anti-Fuse Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 1T1C semiconductor structures occupy a large area, making it challenging to achieve high-density memory cells or redundancy, as each anti-fuse requires a separate control gate.
Innovation Solution
A semiconductor layout structure with a substrate featuring active regions separated by an isolation structure, where conductive structures are embedded within the isolation structure and share source/drain portions with transistors, allowing for a pair of anti-fuse structures to be blown out simultaneously, reducing the size of the unit cell and increasing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional 1T1C structure is used with separate control gate for each anti-fuse, then anti-fuse can be controlled independently, but the unit cell occupies large area
Solution Approach 1:
The patent merges the control function for multiple anti-fuses into a single shared control gate. The control gate is positioned such that it can simultaneously control multiple anti-fuse structures located in different active regions, eliminating the need for separate control gates for each anti-fuse and thereby reducing the unit cell area while maintaining independent controllability through selective activation
Solution Approach 2:
The control gate is designed to serve multiple functions by controlling multiple anti-fuses simultaneously. This multi-functional control gate structure allows a single gate to perform the control function that would otherwise require multiple separate gates, thus reducing the overall area occupied by control structures in the unit cell
2Quantity of substance
If number of anti-fuse is increased for high density memory or redundancy, then memory capacity or reliability is improved, but the area occupied by conventional 1T1C structure increases
Solution Approach 1:
Multiple anti-fuse structures share a common control gate and isolation structure, merging previously separate control elements into shared resources. This allows increasing the number of anti-fuses in a unit cell without proportionally increasing the area, as the control infrastructure is consolidated rather than replicated for each anti-fuse
Solution Approach 2:
The patent utilizes vertical stacking and three-dimensional arrangement of anti-fuse structures around shared control elements. By organizing anti-fuses in multiple layers or spatial configurations that share common control gates, the design increases anti-fuse density without linearly increasing the planar area occupied by control structures
Data Source
AI summary
A semiconductor layout structure includes a substrate, a plurality of gate structures, and a plurality of conductive structures. The substrate includes a plurality of active regions extending along a first direction, in which the active regions are separated from each other by an isolation structure. The transistors are respectively disposed in the active regions. The gate structures extend across the active regions along a second direction that is perpendicular to the first direction, in which each of the active regions includes a pair of source/drain portions at opposite sides of each of the gate structures. The conductive structures are embedded in a first portion of the isolation structure disposed between the adjacent active regions in the first direction, wherein the conductive structures extend along the second direction and are separated from the source/drain portions by the isolation structure.