Semiconductor Layout Generation Using Preliminary Availability Verification
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Solution Overview
Problem
The existing process of generating a layout image for semiconductor device manufacturing is inefficient due to the inability to verify in advance whether the layout image generated through placement and routing (PnR) violates manufacturing limits, leading to potential unusability and increased time requirements.
Innovation Solution
An electronic device with a processor that partitions circuit components into mats, calculates the availability of placement and routing based on limited connecting elements, and performs PnR only when availability is confirmed, allowing for the generation of a usable layout image.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If placement and routing is performed without advance verification, then the layout image can be generated quickly, but the layout image may violate manufacturing limits and become unusable
Solution Approach 1:
The patent performs preliminary verification of manufacturing limits before executing the full placement and routing process. The processor calculates whether placement and routing is available by checking if the number of interconnections between mats exceeds a reference value, and only proceeds with PnR when availability is confirmed, preventing generation of unusable layout images
Solution Approach 2:
The patent enables skipping the time-consuming placement and routing process entirely when the preliminary verification indicates that manufacturing limits would be violated. By calculating availability in advance and comparing interconnection counts against reference values, the system rushes through the verification step and avoids executing PnR for invalid configurations, saving time
2Manufacturing precision
If placement and routing is performed without checking availability, then the process is simpler and faster, but the manufactured semiconductor device may have defects
Solution Approach 1:
The patent extracts the essential verification check from the complex placement and routing process. Instead of performing the entire PnR process and then checking compliance, the system takes out the critical availability calculation step that checks whether the number of interconnections exceeds manufacturing limits, performing this extraction independently before full PnR execution
Solution Approach 2:
The patent performs preliminary calculation of placement and routing availability by counting interconnections between mats and comparing against reference values before executing the full placement and routing process. This preliminary action ensures manufacturing precision is maintained while avoiding the complexity of performing complete PnR verification after the fact
Data Source
AI summary
Disclosed is an operating method of an electronic device that includes a processor and supports manufacture of a semiconductor device. The operating method includes receiving, at the processor, circuit schematics for the manufacture of the semiconductor device, partitioning, at the processor, circuit components of the circuit schematics into at least two mats, calculating, at the processor, availability of placement and routing of the circuit components, based on limited connecting elements electrically connected to the circuit components, for each of the at least two mats, and performing, at the processor, the placement and routing to generate a layout image for the manufacture of the semiconductor device when the availability indicates that the placement and routing is available. The limited connecting elements include vertical lines, which electrically connect an upper portion and a lower portion of the semiconductor device, at limited locations of the semiconductor device.