Semiconductor Layout Design Using Photolithography-Aware Cell Spacing
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Solution Overview
Problem
The existing layout design methods for semiconductor devices are time-consuming and require significant trial and error, especially when incorporating dummy cells, which increases design time and complicates the manufacturing process due to limitations in photolithography resolution.
Innovation Solution
The method involves strategically spacing conductive lines for logic and dummy cells based on photolithography resolution, using different photomasks for adjacent cells and forming conductive patterns in perpendicular directions, thereby reducing the need for additional swapping operations and optimizing the layout design time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If dummy cells are inserted into the semiconductor device layout, then the degree of integration is improved, but the layout design time increases
Solution Approach 1:
The patent applies preliminary action by pre-determining the spacing between conductive lines of adjacent cells before dummy cell insertion. The layout design tool is configured with reference distances that account for photolithography resolution limitations, so that when dummy cells are inserted, the additional swapping operations are minimized or eliminated because the conductive lines are already positioned to accommodate the dummy cells.
2Area of stationary object
If conductive lines are spaced closer together to increase integration density, then the area utilization is improved, but the manufacturing precision deteriorates due to photolithography resolution limits
Solution Approach 1:
The patent applies parameter changes by adjusting the spacing parameter of conductive lines based on photolithography resolution capabilities. Instead of using uniform minimum spacing, the layout design tool implements variable spacing where conductive lines are positioned at distances that are multiples of the photolithography resolution limit. This ensures manufacturability while maximizing area utilization through optimized rather than minimal spacing.
Solution Approach 2:
The patent applies local quality by differentiating the spacing requirements for different regions of the semiconductor device. Conductive lines adjacent to logic cells have different spacing requirements compared to those adjacent to dummy cells. The layout design tool applies local spacing rules based on the cell type and position, allowing tighter spacing where possible while maintaining manufacturing precision where photolithography limitations exist.
3Reliability
If additional swapping operations are performed to accommodate dummy cells, then the layout correctness is improved, but the device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring the layout design tool with reference distances and spacing rules that anticipate dummy cell insertion. The conductive lines are initially positioned considering potential dummy cell locations, so that when dummy cells are inserted, the layout already conforms to correctness requirements without needing additional swapping operations to correct positioning errors.
Data Source
AI summary
A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.