Semiconductor Layout Correction Using Neural Network Estimation
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Solution Overview
Problem
The increasing complexity of integrated circuit designs for semiconductor devices and the optical proximity effect (OPE) caused by light diffraction and interference during photolithography lead to distortion and misalignment issues, making it challenging to accurately implement layouts on semiconductor wafers.
Innovation Solution
A method using machine learning, specifically an artificial neural network (ANN) to measure and estimate misaligned values of patterns in semiconductor devices, allowing for the generation of corrected layouts that account for optical proximity correction and position adjustments, thereby enhancing correction efficiency and reducing the time required for complex structure corrections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional optical proximity correction methods are used to correct layout distortions, then manufacturing precision is improved, but device complexity and correction time increase significantly for highly integrated circuits
Solution Approach 1:
The patent replaces traditional mechanical/optical correction methods with a machine learning-based computational system. An artificial neural network is trained on measured misalignment data from semiconductor wafers and then used to predict and correct layout distortions, substituting complex physical correction processes with intelligent algorithms that reduce computational burden and improve efficiency.
Solution Approach 2:
The patent creates a virtual model of the semiconductor manufacturing process by training an artificial neural network on measured misalignment data. This digital twin or virtual copy allows the system to simulate and predict layout distortions without requiring physical trial-and-error corrections, enabling efficient optimization of the correction process.
2Manufacturing precision
If comprehensive correction of all pattern points is performed, then manufacturing precision is improved, but loss of time increases due to the large number of measurements and calculations required
Solution Approach 1:
The patent measures misalignment data from only a portion of pattern points rather than all points, using this partial data to train the artificial neural network. The trained model then generalizes to predict misalignments for unmeasured points, achieving comprehensive correction with only partial measurements, thus significantly reducing measurement and processing time.
Solution Approach 2:
The patent performs preliminary training of the artificial neural network using measured misalignment data before actual production correction. This pre-training phase creates a ready-to-use correction model that can quickly predict and correct layout distortions during manufacturing without requiring time-consuming real-time measurements and calculations for each new layout.
3Reliability
If more measurement points are used to train the correction model, then reliability of correction is improved, but loss of time and measurement resources increase
Solution Approach 1:
The patent demonstrates that measuring and using data from only a portion of pattern points is sufficient to train an effective correction model. The artificial neural network learns general patterns of misalignment from this partial data and applies them to correct the entire layout, achieving high reliability without the need to measure every single point.
Solution Approach 2:
The artificial neural network, once trained on partial measurement data, serves itself to predict and correct misalignments for unmeasured points. The model internalizes the correction knowledge during training and then autonomously applies it during production, eliminating the need for continuous measurement and manual correction for each new layout.
Data Source
AI summary
In a method of correcting a design layout of a semiconductor device, misaligned values of a portion of points of a target pattern of each of a plurality of regions of interest in a semiconductor device fabricated based on an original layout are measured, misaligned values of unmeasured points of the target pattern are estimated by using an artificial neural network trained based on the measured misaligned values of the portion of points, and a target layout of the semiconductor device is generated by using the estimated misaligned values.