Semiconductor Layout Decomposition for Quadruple Patterning
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Solution Overview
Problem
The quadruple patterning technology (QPT) process for semiconductor device manufacturing is time-consuming due to the complexity of decomposing layouts into four patterns, which hinders the ability to meet design rules for high-density semiconductor devices.
Innovation Solution
A method using a double pattern dividing algorithm from the double patterning technology (DPT) process to decompose semiconductor device layouts into four patterns, involving temporary patterns, target patterns, and decomposed patterns, with pattern dividing operations in both directions to generate masks for substrate patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a layout decomposition method specifically designed for QPT is used, then the decomposition can be completed into four patterns, but the process time increases significantly
Solution Approach 1:
The patent segments the QPT layout decomposition process into multiple intermediate stages: first dividing the layout into two groups, then further dividing each group into two more groups. This segmentation allows the complex four-pattern decomposition to be broken down into manageable steps that can reuse simpler algorithms, thereby reducing overall processing time while maintaining decomposition accuracy.
Solution Approach 2:
The patent performs preliminary actions by first dividing the layout into two groups using a simplified algorithm before proceeding to the final four-group decomposition. This preliminary division prepares the data structure and pattern assignments in advance, making the subsequent decomposition steps more efficient and reducing the computational burden during the actual QPT decomposition process.
2Productivity
If a double pattern dividing algorithm from DPT is reused for QPT, then the decomposition speed increases, but the ability to handle complex four-pattern conflicts may be compromised
Solution Approach 1:
The patent introduces intermediary pattern assignments as a mediator between the simple double-pattern algorithm and the complex quadruple patterning requirements. By assigning patterns in intermediate steps and using these assignments to guide further decomposition, the system maintains the speed advantages of simpler algorithms while ensuring that all four-pattern conflict requirements are satisfied through multiple passes of the decomposition process.
Data Source
AI summary
A method of decomposing a layout of a semiconductor device for a quadruple patterning technology (QPT) process includes dividing the layout of the semiconductor device into a first temporary pattern, which includes rectangular features having a rectangular shape, and a second temporary pattern, which includes cross couple features having a Z-shape, generating a third temporary pattern and a fourth temporary pattern by performing a pattern dividing operation on the first temporary pattern in a first direction, generating a first target pattern and a second target pattern by incorporating each of the cross couple features included in the second temporary pattern into one of the third temporary pattern and the fourth temporary pattern, and generating first through fourth decomposed patterns by performing the pattern dividing operation on the first target pattern and the second target pattern in a second direction.