Semiconductor Layout Design Method for Reducing Turn Around Time
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Solution Overview
Problem
The existing method for designing semiconductor integrated circuits with separating well regions requires separate processes for forming the well region and connecting power supply, leading to increased design time, complexity, and potential design errors due to unsatisfactory intervals between basic cells and well regions.
Innovation Solution
A layout method and tool that prepare and place first and second cell patterns with transistors and deep wells on semiconductor substrates, allowing for simultaneous formation of regions with different potentials, thereby integrating the well region design into the same process as basic cell placement, reducing design time and improving quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a separating well region is formed to electrically separate the well region from the substrate, then the threshold voltage can be increased and power consumption reduced, but the design process becomes more complex and requires separate processes for well formation and power supply connection
Solution Approach 1:
The patent merges the separating well region formation with the basic cell placement process by integrating the well region definition into the cell pattern data structure. This allows the well region to be automatically formed during the same process that places basic cells, eliminating the need for separate well formation and power supply connection processes.
Solution Approach 2:
The patent performs preliminary action by pre-defining the separating well region boundaries and power supply connection points within the cell pattern data before placement. This allows the well region to be automatically configured during cell placement without requiring subsequent separate design steps for well formation and electrical connection.
2Reliability
If a separating well region is inserted after basic cell placement, then regions with different potentials can be formed, but the interval between basic cells and well region may not satisfy design standards requiring redesign
Solution Approach 1:
The patent combines the well region placement with basic cell placement in a single automated process. The cell pattern data includes both basic cell positions and separating well region boundaries, allowing simultaneous placement that ensures proper intervals are maintained from the beginning, eliminating the need for redesign.
Solution Approach 2:
The patent implements feedback by having the layout design tool automatically verify that the intervals between basic cells and separating well regions satisfy design standards during the placement process. If standards are not met, the tool can adjust the placement automatically, preventing the need for subsequent redesign.
3Ease of manufacture
If separate processes are used for basic cell placement and separating well region formation, then each process can be optimized independently, but the overall design time increases and requires additional processes
Solution Approach 1:
The patent merges the basic cell placement process and separating well region formation into a single integrated automated process. The cell pattern data structure contains both basic cell positions and well region boundaries, allowing the layout design tool to perform both functions simultaneously, thereby improving design speed without sacrificing process optimization.
Solution Approach 2:
The patent makes the cell pattern data structure universal by enabling it to define both basic cells and separating well regions within the same data structure. This allows the layout design tool to handle both functions with a single process, improving productivity while maintaining the ability to optimize each function independently through the unified data structure.
Data Source
AI summary
Design time (TAT) is reduced in a layout design of a semiconductor integrated circuit having a well supplied with a potential different from a substrate potential. A layout design method of the present invention includes preparing a first cell pattern placed on a semiconductor substrate of a first conductive type, preparing a second cell pattern having a deep well of a second conductive type, placing the first cell pattern in a first circuit region, and placing the second cell pattern in a second region different from the first circuit region. This reduces TAT in chip design.