Semiconductor Layout Dummy Feature Insertion for Lithography
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Solution Overview
Problem
Modern semiconductor device fabrication faces challenges in reproducing layout designs on wafers due to light diffusion causing shape distortions, particularly width variations in features, which affect the accuracy of timing and frequency parameters in IC chips.
Innovation Solution
The method involves inserting dummy features into the initial layout and assigning both target and dummy features to multiple masks based on specific mask-assignment rules to generate a final layout that minimizes width variations by controlling the placement and coloring of features during the lithography process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If multi-patterning lithography is used to generate sub-resolution features, then the feature size can be reduced below the lithography resolution limit, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies segmentation by decomposing the initial layout into multiple targets and assigning them to different masks through layout coloring. This allows sub-resolution features to be generated through multiple patterning steps, achieving feature sizes below the lithography resolution limit while managing process complexity through systematic decomposition
Solution Approach 2:
The patent performs preliminary retargeting of the layout before actual fabrication. By adjusting shapes in the layout in advance to correct for manufacturing idiosyncrasies like light diffusion, the system prepares the design to account for expected distortions, thereby achieving the desired final feature dimensions despite the complex multi-patterning process
2Manufacturing precision
If layout shapes are adjusted for better printability, then the manufacturing accuracy improves, but the design complexity increases
Solution Approach 1:
The patent performs retargeting as a preliminary action before fabrication, adjusting layout shapes in advance to compensate for manufacturing idiosyncrasies such as light diffusion causing sharp corners to appear round. This preliminary adjustment ensures better printability and manufacturing accuracy without requiring complex real-time corrections during production
Solution Approach 2:
The patent creates a retargeted layout that serves as a corrected copy of the original design. This retargeted version incorporates adjustments for manufacturing effects, allowing the fabrication process to produce accurate features while the original design intent is preserved in the retargeted copy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces width variations in fabricated features, ensuring that the final dimensions of semiconductor devices align closely with the original design, thereby improving the accuracy of timing and frequency parameters in IC chips.
Implementation Method 1
light may diffuse to cause a sharp corner of a shape in the layout to appear round on the wafer
Data Source
AI summary
Systems and methods are provided for designing semiconductor device layouts. For example, an initial layout including multiple target features associated with semiconductor devices is received. One or more dummy features are determined to be inserted into the initial layout. The target features and the dummy features are assigned to multiple masks based at least in part on one or more mask-assignment rules. A final layout is generated for fabricating the semiconductor devices.