Semiconductor Layout Dummy Seed Generation for CMP Planarity

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Solution Overview

Problem

The existing methods for achieving planarity on semiconductor wafers through the CMP process are time-consuming, require significant computing resources, and are difficult to manage, especially in achieving a suitable pattern density for effective polishing.

Innovation Solution

A method and system for generating a semiconductor device array layout by using a processor to integrate dummy seeds from various pattern density templates into the layout, allowing for the determination and achievement of a target pattern density, which aids in standardized polishing of the wafer surface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If dummy units are inserted manually using conventional methods, then pattern density can be adjusted, but the process becomes time-consuming and requires significant computing resources

Engineering Contradiction:

Improvepattern density controlVSAvoiddummy insertion time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent changes the parameter of dummy unit configuration by providing a library of pre-designed dummy units with different pattern densities. Instead of manually inserting individual dummy units, the system selects and inserts entire pre-configured dummy units based on the required pattern density, thereby reducing the time and computing resources needed for dummy insertion while maintaining precise pattern density control

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies preliminary action by pre-designing and storing multiple dummy unit configurations with different pattern densities in a database before the actual layout design process. This allows the system to quickly select and insert the appropriate pre-configured dummy units during layout creation, eliminating the need for time-consuming manual dummy unit insertion and computing-intensive real-time calculations

Inventive Principle:

Principle #10Preliminary action

2Reliability

If numerous dummy units are inserted to achieve suitable pattern density, then polishing uniformity improves, but computational resources and processing time increase significantly

Engineering Contradiction:

Improvepolishing uniformityVSAvoidlayout complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the parameter of layout complexity by introducing a library of pre-configured dummy units with different pattern densities. Instead of inserting numerous individual dummy units, the system selects from a limited set of pre-designed dummy unit configurations, thereby maintaining polishing uniformity through appropriate pattern density while reducing the overall complexity of the layout design process

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies segmentation by dividing the dummy unit insertion process into discrete, pre-configured units with different pattern densities. Instead of treating dummy insertion as a continuous optimization problem requiring numerous individual units, the system segments the solution into a finite library of dummy unit types, making the process more manageable and computationally efficient while still achieving the desired polishing uniformity

Inventive Principle:

Principle #1Segmentation

3Manufacturing precision

If conventional dummy insertion methods are used, then pattern density can be adjusted, but it is difficult to estimate the achieved pattern density before completion

Engineering Contradiction:

Improvepattern density adjustmentVSAvoidpattern density estimation

Core Design Contradiction:

Manufacturing precisionVSDifficulty of detecting and measuring

Solution Approach 1:

The patent applies feedback by implementing a system that calculates and provides real-time information about the achieved pattern density during the dummy unit insertion process. The system monitors the insertion of pre-configured dummy units and continuously updates the pattern density estimation, allowing operators to see the current status and make adjustments if needed, thereby making pattern density estimation straightforward and controllable

Inventive Principle:

Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the process of achieving a suitable pattern density, reducing computational resources and time, while ensuring consistent planarity and improved polishing efficiency.

Implementation Method 1

Two common techniques used to achieve planarity on a semiconductor surface are the Spin-On Glass (SOG) etchback process and the Chemical Mechanical Polishing (CMP) process

Methodology Applied

Scientific EffectChemical Mechanical Polishing:

Data Source

PatentUS7512924B2Semiconductor device structure and methods of manufacturing the same

Publication Date: 2009.03.31 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.