Semiconductor Layout Method Dynamic Wiring Position Selection
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Solution Overview
Problem
As the degree of integration in semiconductor devices increases, existing methods for arranging wirings between semiconductor elements lack sufficient design freedom and efficiency, leading to reduced performance and increased resistance and parasitic capacitance.
Innovation Solution
The semiconductor device and layout method involve selecting positions for input and output lines connecting gate structures and active regions from a plurality of candidates, rather than predefining these positions, thereby increasing design freedom and efficient wiring arrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wiring positions are predefined in standard cells, then manufacturing precision is improved, but design freedom is reduced
Solution Approach 1:
The patent makes wiring positions dynamic by allowing selection from multiple candidate positions rather than using fixed predefined positions. The wiring position selection unit dynamically determines optimal positions based on design requirements, resolving the contradiction between manufacturing precision and design freedom.
Solution Approach 2:
The patent changes the parameter of wiring position from a fixed value to a selectable set of candidate positions. By providing multiple candidate positions and allowing dynamic selection, the system maintains manufacturing precision while significantly improving design freedom and adaptability.
2Device complexity
If wiring positions are predefined in standard cells, then device complexity is reduced, but resistance and parasitic capacitance increase
Solution Approach 1:
The patent introduces dynamic wiring position selection to optimize electrical performance. By dynamically choosing wiring positions from multiple candidates based on resistance and parasitic capacitance considerations, the system reduces electrical losses while maintaining manageable layout complexity through automated selection.
Solution Approach 2:
The patent changes wiring position from a fixed parameter to a selectable parameter with multiple candidate values. This allows optimization of electrical characteristics (reducing resistance and parasitic capacitance) while the standard cell framework maintains reasonable device complexity.
3Adaptability or versatility
If wiring positions are selected from multiple candidates, then design freedom is improved, but manufacturing precision is reduced
Solution Approach 1:
The patent segments the wiring position into multiple discrete candidate positions that are pre-defined at precise locations. This segmentation allows design freedom in selecting among candidates while each candidate maintains precise manufacturing specifications, resolving the contradiction between design flexibility and manufacturing precision.
Data Source
AI summary
A semiconductor device according to an embodiment of the present inventive concept includes a plurality of standard cells in a first direction and a second direction, parallel to an upper surface of a substrate and intersecting with each other, and each of the plurality of standard cells having one or more gate structures and one or more active regions, and in some standard cells providing the same circuit and in standard cell regions at different locations, input lines or/and output lines are at different locations.