Semiconductor Layout Verification Using Filter Marks
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Solution Overview
Problem
The existing semiconductor manufacturing techniques are inefficient due to the time-consuming nature of design rule checking and optical proximity correction (OPC) processes, which are exacerbated by the need to re-run these tests and OPC cycles whenever layouts are updated, leading to increased cycle time and human loading.
Innovation Solution
A method is introduced that creates a library for test patterns and filter marks to identify and filter out ignorable hot spots, allowing for targeted OPC verification and reducing the number of hot spots that need to be checked, thereby streamlining the OPC cycle and design rule checking processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If comprehensive DRC and OPC verification is performed on all layouts, then manufacturing precision is improved, but productivity deteriorates due to increased cycle time
Solution Approach 1:
The layout is segmented into frame regions and main chip regions, with different verification strategies applied to each. The frame region contains test patterns that are verified separately from the main chip layout, allowing parallel processing and reducing overall verification time while maintaining comprehensive coverage.
Solution Approach 2:
Test patterns are pre-configured in the frame region before main chip layout verification. The library of test patterns is created in advance, and filter marks are pre-defined to automatically exclude known good patterns from hot spot analysis, reducing the verification workload for subsequent OPC cycles.
2Manufacturing precision
If all hot spots are checked and repaired, then manufacturing precision is improved, but productivity deteriorates due to increased human loading
Solution Approach 1:
Filter marks are used to extract and exclude test pattern hot spots from the main verification process. These filter marks identify regions containing test patterns that should not be treated as actual layout defects, automatically removing them from hot spot repair requirements and reducing manual intervention needs.
Solution Approach 2:
The frame region acts as an intermediary containing test patterns that mediate between the design verification process and the main chip layout. By isolating test pattern verification in the frame, the system can automatically handle these patterns without requiring manual hot spot analysis, reducing human loading while maintaining verification quality.
3Manufacturing precision
If layouts are updated and re-verified, then manufacturing precision is maintained, but productivity deteriorates due to repeated OPC cycles
Solution Approach 1:
Instead of verifying the entire layout including frame regions during each OPC cycle, the verification approach is inverted: the frame region with test patterns is verified separately and pre-configured, allowing the main chip layout to be verified more quickly during OPC iterations. This inversion reduces the scope of repeated verification while maintaining overall layout quality.
Data Source
AI summary
A method of designing a semiconductor device includes creating a library for test patterns on a frame and an on purpose violation layout on a main chip of a layout, and then creating filter marks according to the library. An OPC (optical proximity correction) is run using the layout, and an OPC verifying is performed for obtaining a pattern with hot spots to determine whether the hot spots are within the frame and the filter marks. When the hot spots are within the frame and the filter marks, a mask can be made. When the hot spots are outside the frame and the filter marks, it is necessary to check whether the hot spots need to be repaired. When the hot spots are within the frame and outside the filter marks, the hot spots are added into the library as data of the on purpose violation layout.