Semiconductor Layout Decomposition via Interference Mapping
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Solution Overview
Problem
The down-scaling of integrated circuits requires more precise photolithographic processes to form fine patterns on wafers, but existing methods face challenges in managing optical interference and maintaining exposure margins, leading to limitations in pattern formation and yield.
Innovation Solution
A method of decomposing semiconductor device layouts into patterns influenced by constructive interference, using interference mapping to generate specific illumination methods and apertures for each pattern type, allowing for the separation of patterns into sub-patterns that optimize photolithographic processes and increase exposure margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing photolithographic methods are used for down-scaling, then fine patterns can be formed, but optical interference management becomes difficult and exposure margins decrease
Solution Approach 1:
The patent divides the pattern layout into multiple sub-patterns based on their optical interference characteristics. By segmenting the overall pattern into groups with similar interference behaviors, the method enables optimized illumination conditions for each subgroup, thereby maintaining high manufacturing precision while improving exposure margins through targeted optical control.
Solution Approach 2:
The patent applies different illumination conditions and optical parameters to different regions of the pattern layout based on their specific interference characteristics. Each sub-pattern receives localized optical optimization, allowing fine patterns in high-precision areas to be formed while maintaining adequate exposure margins through region-specific control rather than uniform processing.
2Adaptability or versatility
If patterns are decomposed into sub-patterns with different illumination methods, then photolithographic process flexibility increases, but process complexity increases
Solution Approach 1:
The patent segments the pattern layout into sub-patterns that can be processed with different illumination methods, enabling flexible adaptation to various optical conditions. This segmentation allows the system to handle diverse pattern types with optimized illumination while managing complexity through systematic classification and automated assignment of processing parameters.
Solution Approach 2:
The patent implements dynamic illumination condition assignment based on the specific characteristics of each sub-pattern. The illumination method is not fixed but adapts dynamically to the pattern type, allowing the photolithographic process to flexibly adjust parameters such as numerical aperture and illumination angle for optimal results while maintaining manageable complexity through algorithmic control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the flexibility and stability of photolithographic processes, ensuring reliable pattern formation and improving yield by optimizing the influence of constructive interference on different pattern types.
Implementation Method 1
generating a first interference map for the pattern layout, the first interference map including optical interference information regarding the first and second patterns
Implementation Method 2
Generating the second interference map may include illuminating the first decomposition pattern layout using a cross-pole light source or a quasar light source
Data Source
AI summary
Embodiments relate to a method of decomposing a layout of a semiconductor device. The method may include generating a pattern layout including first patterns and second patterns, generating an interference map for the pattern layout, the interference map including optical interference information regarding the first and second patterns, and decomposing the pattern layout into a first decomposition pattern layout including the first patterns, and a second decomposition pattern layout including the second patterns, based on the interference map. In the interference map, an influence of constructive interference on the first patterns may be greater than an influence of constructive interference on the second patterns.