Semiconductor Component Layout Routing for IR Drop Control

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Solution Overview

Problem

Current IC layout methods fail to account for parasitic resistance and capacitance in the middle-end and back-end of line, leading to performance degradation and requiring time-consuming adjustments after layout implementation.

Innovation Solution

Implement a method that includes pre-layout simulation, post-layout simulation, and iterative routing adjustments to control parasitic resistance within predetermined thresholds, ensuring acceptable performance without enlarging the IC area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If automated placement and routing (APR) tools are used for IC layout implementation, then layout generation efficiency is improved, but voltage drop (IR drop) increases due to parasitic resistance/capacitance in MEOL/BEOL

Engineering Contradiction:

Improvelayout generation efficiencyVSAvoidIC performance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by performing pre-layout simulation to predict and verify IC performance before actual layout implementation. This allows potential IR drop issues to be identified and addressed in the design phase, preventing performance degradation after layout is generated by the APR tools.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms through post-layout simulation that measures actual IR drop and compares it against targets. The system then provides feedback to adjust routing and component placement to reduce parasitic effects, creating a closed-loop optimization process that maintains IC performance while using automated layout generation.

Inventive Principle:

Principle #23Feedback

2Reliability

If IC area is enlarged to improve performance, then voltage drop is reduced, but device size increases

Engineering Contradiction:

ImproveIC performanceVSAvoidIC area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies parameter changes by optimizing routing parameters (such as wire width, layer selection, and routing density) to reduce parasitic resistance and capacitance. By changing these routing parameters rather than simply enlarging the IC area, the system achieves reduced IR drop while maintaining compact device dimensions.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If layout is adjusted after implementation to reduce IR drop, then IC performance is improved, but development time increases

Engineering Contradiction:

ImproveIC performanceVSAvoiddevelopment time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary performance verification through pre-layout simulation before final layout implementation. This early detection and correction of potential IR drop issues prevents time-consuming iterative adjustments after layout completion, reducing overall development time while ensuring IC performance.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system implements efficient feedback loops through automated post-layout simulation and analysis. Rather than manual adjustments, the system automatically analyzes IR drop measurements and provides targeted routing adjustments, significantly reducing the time required for performance optimization compared to traditional iterative design processes.

Inventive Principle:

Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Reduces the performance gap between pre-layout and post-layout simulations by controlling parasitic resistance, maintaining IC performance without resizing devices or increasing area, thus optimizing the layout process.

Implementation Method 1

a first conductive via connecting the first conductive segment to the second conductive segment

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

an extra voltage drop (e.g. IR drop, indicating the voltage drop due to the current (I) and the resistance (R)) caused by parasitic resistance/capacitance

Methodology Applied

Scientific EffectParasitic resistance: Electrical Resistance

Data Source

PatentUS20260111643A1Method and non-transitory computer-readable medium for arranging components within a semiconductor device

Publication Date: 2026.04.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure provides a method and a non-transitory computer-readable medium for arranging components within a semiconductor device. The method includes providing a plurality of electrical components in a pre-layout, generating a first layout by routing the plurality of electrical components, obtaining a first resistance between a power terminal of the first layout and a first terminal of a first electrical component in the first layout, comparing the first resistance and a first threshold, adjusting routing of the first layout such that the first resistance is less than the first threshold, and generating a tape out file for the semiconductor device according to the first layout.