Semiconductor Layout Design for Leakage Current and Antenna Effect Control
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Solution Overview
Problem
As semiconductor devices shrink in size, they face challenges such as max transition time violation, wiring congestion, and gate oxide breakdown due to the antenna effect when applying multi-fanout and super cut-off technologies, which affect power consumption and leakage current in sleep mode.
Innovation Solution
A method of designing semiconductor devices using electronic design automation (EDA) tools, which includes generating an improved layout pattern for pre-routing lines that connect buffers to head circuits, performing clock tree synthesis, and optimizing signal line layouts to reduce leakage current and prevent antenna effects, while ensuring efficient resource use and minimizing transition time violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multi-fanout and super cut-off technology are applied to reduce power consumption and leakage current, then power efficiency is improved, but max transition time violation, wiring congestion, and gate oxide breakdown due to antenna effect occur
Solution Approach 1:
The patent segments the power line into multiple sections with separate via connections to different ground points. This segmentation distributes the antenna effect across multiple smaller segments rather than concentrating it in a single long power line, thereby preventing gate oxide breakdown while maintaining the super cut-off functionality for reducing leakage current.
Solution Approach 2:
The patent introduces intermediate via connections that act as mediators between the power line and ground. These via connections provide multiple discharge paths for accumulated charges, preventing excessive voltage buildup that would cause gate oxide breakdown, while still allowing the power-gating circuit to effectively control leakage current.
2Ease of manufacture
If pre-routing lines are optimized before signal line routing, then wiring congestion is reduced, but design complexity increases
Solution Approach 1:
The patent performs preliminary routing of pre-routing lines (power lines and control lines) before routing the signal lines. This preliminary action reserves appropriate spaces for power distribution and control signals, preventing wiring congestion in later stages while using systematic EDA tools to manage the increased design process complexity.
3Use of energy by moving object
If power-gating circuit is used to reduce power consumption, then energy efficiency is improved, but max transition time violation occurs
Solution Approach 1:
The patent applies different quality characteristics to different parts of the power-gating circuit. The power line is designed with multiple via connections for stable voltage supply, while the control line is optimized for fast signal transmission. This local quality differentiation allows the circuit to achieve both low power consumption and acceptable transition times by optimizing each component for its specific function.
Data Source
AI summary
A method of designing a semiconductor device including a memory device, a buffer, and a plurality of head circuits connected to the buffer is disclosed. The method includes generating a layout pattern of a power line of the semiconductor device, generating an improved layout pattern of a pre-routing line that connects the buffer to the head circuits, and generating a layout pattern of signal lines of the semiconductor device. The signal lines include both normal signal lines and signal lines for a central clock of the semiconductor device. A layout of the semiconductor device includes a plurality of layers.