Semiconductor Layout for Multi-Fin Speed and Leakage Control
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Solution Overview
Problem
Multi-fin FETs suffer from higher leakage and power consumption compared to single-fin FinFETs, hindering the achievement of both high switching speed and low power consumption in semiconductor devices.
Innovation Solution
The implementation of multi-fin and mono-fin active regions with optimized gate structures, source/drain features, and isolation techniques, including the use of high-K metal gate stacks and dielectric materials, to enhance performance and reduce leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multi-fin FETs are used to achieve high switching speed, then switching speed is improved, but power consumption increases due to higher leakage
Solution Approach 1:
The device is divided into multiple fins within a single FET structure, allowing the channel to be segmented into parallel conduction paths. This segmentation increases the effective channel width and drive current for high switching speed while maintaining individual fin control to manage leakage through optimized fin spacing and isolation structures.
Solution Approach 2:
Different regions of the multi-fin FET are given different properties: the fin width, spacing, and depth are locally optimized to balance drive current and leakage. The source/drain regions are selectively doped in different areas, and isolation structures are placed at specific locations between fins to suppress leakage while preserving high-speed performance in critical regions.
2Reliability
If fin width is reduced to achieve short channel control, then short channel control is improved, but source/drain contact landing area decreases leading to higher contact resistance
Solution Approach 1:
The solution moves from a two-dimensional contact problem to three dimensions by forming raised source/drain structures and using sidewall spacers to create vertical contact paths. The contact landing area is extended in the vertical dimension through elevated S/D regions, allowing adequate contact area even when the horizontal fin width is reduced for better short channel control.
Solution Approach 2:
Source/drain extensions are formed preliminarily before the main source/drain regions, creating a graded transition that reduces contact resistance. The sidewall spacers are formed in advance to define the final contact dimensions and ensure proper alignment, allowing the contact structure to be optimized independently of the fin dimensions.
Data Source
AI summary
A semiconductor structure includes: an isolation feature and a first device on a first side of the isolation feature. The first device includes: a first plurality of fins, a first gate structure extending across the first plurality of fins, and a first source/drain contact disposed over the first plurality of fins. The semiconductor structure includes a second device on a second side of the isolation feature opposite the first side. The second device includes: a first fin aligned with one of the first plurality of fins along a first direction, a second gate structure extending across the first fin, and a second source/drain contact disposed over the first fin.