Semiconductor Design Layout Marking for Double Patterning Lithography
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Solution Overview
Problem
Conventional double patterning lithography (DPL) techniques for semiconductor device manufacturing do not adequately consider factors beyond minimum spacing design rules, such as device criteria, processing constraints, and environmental variations when decomposing design layouts for photomasks, leading to inefficiencies and inaccuracies in pattern formation.
Innovation Solution
A method is introduced where design layouts for semiconductor devices are marked at the design level to account for device criteria, processing constraints, and environmental factors, allowing for more informed decomposition into multiple photomasks, with specific features and stitching locations designated for each mask to ensure accurate and efficient pattern formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the mask foundry decomposes the design layout based only on minimum spacing design rules, then the decomposition process is simple and fast, but the pattern formation accuracy and device performance deteriorate due to lack of consideration for device criteria and processing constraints
Solution Approach 1:
The design layout is pre-marked with designations indicating which features should be formed on the first photomask and which on the second photomask, before the decomposition process. This preliminary marking allows the mask foundry to perform decomposition that considers device criteria and processing constraints without significantly increasing the actual decomposition processing complexity, as the guidance information is already in place.
2Productivity
If the mask foundry considers multiple factors (device criteria, processing constraints, environmental variations) during decomposition, then the pattern accuracy and yield improve, but the decomposition time and processing cost increase
Solution Approach 1:
By pre-marking the design layout with photomask assignments and stitching location designations, the complexity of considering multiple factors during decomposition is reduced. The decomposition process can proceed more efficiently since the guidance information is already provided, reducing the time needed for analysis and decision-making during the actual decomposition step.
Solution Approach 2:
The marked design layout provides feedback information to the mask foundry about optimal decomposition choices, allowing them to consider device criteria and processing constraints without performing exhaustive analysis. This feedback mechanism enables higher yield patterns while reducing processing time compared to trial-and-error approaches.
3Reliability
If the design layout is decomposed without considering environmental factors and processing constraints, then the decomposition is straightforward, but design rule violations occur and pattern accuracy decreases
Solution Approach 1:
The design layout is pre-marked with designations that indicate which features should be assigned to which photomask based on device criteria and processing constraints. This preliminary action makes the decomposition process easier to execute correctly, as the markings guide the decomposition while ensuring compliance with design rules and avoidance of violations.
Data Source
AI summary
Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.