Semiconductor Layout Splitting for Overlay-Tolerant Merged Patterns
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Solution Overview
Problem
The double patterning technique in semiconductor fabrication faces challenges with overlay control and alignment, leading to issues such as broken lines and merged connections, which result in serious open or short circuits due to inaccuracies in the decomposition of high-density circuit patterns into lower density sets.
Innovation Solution
A method involving the decomposition of semiconductor layouts into connection patterns and to-be-split patterns, where the to-be-split pattern is split into cutting and counterpart cutting portions, with the boundary line between them moved to form modified cutting and counterpart cutting portions, ensuring no disconnection between outer lines of the merged pattern, thus improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning technique is used to fabricate high-density circuit patterns, then the minimum pattern distance is enlarged, but overlay control and alignment accuracy deteriorate
Solution Approach 1:
The patent segments the high-density circuit pattern into two separate low-density circuit patterns that can be fabricated using conventional photolithography. By dividing the original pattern into multiple sets with larger spacing, the segmentation principle enables the use of standard alignment processes while still achieving the desired high-density final pattern through merging
Solution Approach 2:
The patent introduces dummy patterns and adjustment structures during the preliminary layout stage to compensate for potential overlay errors. These preliminary actions include adding dummy connection patterns and adjusting pattern dimensions before fabrication, which help maintain alignment accuracy throughout the double patterning process
2Ease of manufacture
If high-density circuit patterns are decomposed into lower density sets, then the pattern fabrication becomes feasible, but alignment errors increase leading to disconnection or connection issues
Solution Approach 1:
The patent incorporates dummy connection patterns and overlapping regions as cushioning measures before the actual patterning process. These additional patterns create buffer zones that absorb alignment variations, ensuring that even if overlay errors occur, the critical circuit connections remain intact and reliable
Solution Approach 2:
The patent uses dummy patterns and intermediate connection structures as mediators between the decomposed circuit patterns. These intermediary elements facilitate reliable connections by providing alternative pathways and reducing the direct impact of alignment errors on critical circuit interconnections
3Manufacturing precision
If multiple exposure processes are used in double patterning, then high-density patterns can be formed, but process complexity increases
Solution Approach 1:
The patent employs a unified process flow that handles both the decomposition and merging of patterns through standard photolithography and etching steps. The same fabrication equipment and process parameters are used throughout, making the multi-step process as efficient as possible and reducing the practical complexity despite multiple exposure processes
Data Source
AI summary
A semiconductor structure, including a plurality of connection patterns disposed on the substrate, and a merged pattern disposed between adjacent two of the connection patterns, wherein the merged pattern includes a first outer line, a central line and a second outer line sequentially arranged along a first direction and connected with each other, and an end surface of the first outer line, an end surface of the central line and an end surface of the second outer line are misaligned along the first direction.