Semiconductor Layout Mesh Generation for TCAD Simulation Accuracy
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Solution Overview
Problem
Current semiconductor device design processes face inefficiencies in accurately simulating and refining meshes for three-dimensional simulations, leading to reduced numerical calculation accuracy and increased computational time, especially when handling complex layouts and structures.
Innovation Solution
A TCAD system that includes a layout processing unit to extract vertex coordinates, an initial mesh generation unit to generate meshes passing through these coordinates, and a simulator unit to execute simulations based on process flow and layout data, with mesh refinement capabilities to adapt to specific simulation regions and structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional mesh generation methods are used for three-dimensional simulations, then computational time is reduced, but numerical calculation accuracy deteriorates due to mesh shifting from layout edges
Solution Approach 1:
The patent applies preliminary action by extracting vertex coordinates of layout graphics before mesh generation and using these coordinates to guide the mesh creation process. The mesh generation unit generates meshes that pass through the pre-extracted vertex coordinates, ensuring meshes align with layout edges from the outset rather than correcting shifts afterward. This preliminary coordination between layout data and mesh generation prevents accuracy deterioration while maintaining computational efficiency.
2Measurement precision
If mesh refinement is performed for complex layouts and structures, then simulation accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent applies local quality by implementing mesh refinement specifically in regions containing graphics or structures of interest, rather than uniformly refining the entire mesh. The refinement unit identifies specific regions requiring higher accuracy and applies refined meshes only to those areas. This localized approach maintains high simulation accuracy for critical regions while avoiding the computational overhead of refining the entire device structure.
Solution Approach 2:
The patent applies segmentation by dividing the mesh generation and refinement process into distinct stages: initial mesh generation based on layout vertex coordinates, identification of regions requiring refinement, and targeted refinement of specific segments. This segmentation allows the system to handle complex layouts by breaking them into manageable regions that can be processed independently, reducing overall computational complexity.
3Productivity
If meshes are generated without coordinating with layout vertex coordinates, then generation speed is improved, but mesh alignment with layout edges deteriorates
Solution Approach 1:
The patent applies self-service by having the mesh generation unit automatically use the vertex coordinates extracted from the layout graphics to guide its own mesh generation process. The system extracts layout vertex coordinates and feeds them directly into the mesh generation algorithm, which automatically adjusts mesh placement to pass through these coordinates. This self-coordinating mechanism ensures both layout alignment and generation efficiency without requiring manual intervention or complex external coordination.
Data Source
AI summary
According to an embodiment, a process simulator has a layout processing unit to extract vertex coordinates of a first graphic of a layout of a semiconductor device described in a layout file used for a simulation, an initial mesh generation unit to generate a first initial mesh passing through the vertex coordinates in a plane direction of the layout, and a simulator unit to execute a process simulation of the semiconductor device based on simulation data in which a process flow of the semiconductor device is described, the layout, and the first initial mesh.