Semiconductor Layout Design Using Odd-Multiple Gate Widths
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Solution Overview
Problem
The challenge in designing semiconductor device layouts using the self-align double patterning (SADP) process is meeting constraint conditions for forming fine patterns and high integration, as existing methods struggle to efficiently allocate and adjust standard cell areas to adhere to gate generation rules, leading to errors and increased costs.
Innovation Solution
A method and system for designing semiconductor device layouts that involve receiving chip size and unit placement width information, allocating input and output areas, and adjusting standard cell area widths to be odd multiples of the unit placement width, using a gate generation module and placement and interconnection tools to ensure compliance with SADP process constraints, thereby forming an even number of gates to prevent additional correction processes and reduce errors and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard cell area width is not adjusted to odd multiples of unit placement width, then layout design is simpler, but gate generation rule is violated causing additional correction processes and increased costs
Solution Approach 1:
The patent applies parameter changes by systematically adjusting the width of standard cell areas to conform to specific mathematical relationships (odd multiples of unit placement width). This transformation of dimensional parameters ensures compliance with gate generation rules, eliminating the need for additional correction processes while maintaining manufacturability.
Solution Approach 2:
The patent implements preliminary action by incorporating width adjustment operations during the layout design phase itself, rather than addressing non-compliance issues during manufacturing. The design system proactively ensures that standard cell areas satisfy the required dimensional constraints before fabrication, preventing subsequent correction processes.
2Reliability
If SADP process constraints are not met, then design implementation is easier, but manufacturing errors increase and costs rise
Solution Approach 1:
The patent employs feedback mechanisms through automated design verification systems that check whether standard cell area widths satisfy the required constraints. The system provides feedback during the design process, allowing real-time adjustment to ensure SADP process compliance, thereby preventing manufacturing errors before they occur.
Solution Approach 2:
The patent applies preliminary action by validating layout designs against SADP process constraints during the design phase rather than during manufacturing. The design system pre-checks dimensional parameters and adjusts layouts accordingly, ensuring manufacturability and reducing errors before production begins.
3Adaptability or versatility
If gate generation rule is not followed, then layout design is more flexible, but additional correction processes are required increasing costs
Solution Approach 1:
The patent utilizes parameter changes to transform standard cell area dimensions into values that satisfy the gate generation rule (odd multiples of unit placement width). This systematic parameter adjustment maintains design flexibility while ensuring rule compliance, eliminating the need for costly post-manufacturing corrections.
Data Source
AI summary
A method of designing a layout of a semiconductor device includes receiving information on a size of a target chip and a unit placement width for forming a gate line through a self-align double patterning process by a layout design system. The method also includes allocating an input and output area, a hard macro area, and a standard cell area at the target chip, and adjusting a width of the standard cell area by applying a gate generation rule for setting a width of at least one cell row located in the standard cell area to an odd number multiple of the unit placement width. The unit placement width corresponds to a width between centers of a pair of gate lines in the self-align double patterning process.