Semiconductor Layout OPC for Double Patterning Overlay Accuracy

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Solution Overview

Problem

The double patterning technique (DPT) in semiconductor fabrication faces challenges with overlay control and alignment, leading to issues like disconnection or short circuits due to decomposing high-density circuit patterns into lower density sets, which results in overlay errors and inaccurate alignment.

Innovation Solution

The method employs optical proximity correction to modify the semiconductor layout, expanding connection patterns to form photomasks that prevent significant light diffraction and improve pattern accuracy, allowing for more reliable electrical connections between metal lines and conductive pads without additional photolithography steps, even when patterns violate photolithography rules.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If double patterning technique is used to decompose high-density circuit patterns into lower density sets, then the minimum pattern distance on mask aligner is enlarged, but overlay control and alignment accuracy deteriorate

Engineering Contradiction:
Improveminimum pattern distanceVSAvoidoverlay control and alignment accuracy
Core Design Contradiction:
Manufacturing precisionVSMeasurement precision

Solution Approach 1:

The patent applies optical proximity correction (OPC) as a preliminary action before photolithography to pre-compensate for diffraction effects and pattern deformation. By modifying the mask pattern in advance based on predicted optical effects, the final developed pattern achieves better alignment accuracy and overlay control, resolving the contradiction between pattern decomposition and alignment precision

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback mechanism where the actual pattern formation results are measured and used to adjust subsequent patterning processes. Through iterative optimization based on measured overlay errors and alignment deviations, the system continuously improves pattern accuracy, compensating for the inherent alignment challenges of double patterning

Inventive Principle:
Principle #23Feedback

2Quantity of substance

If connection patterns with dimensions and pitches violating photolithography rules are used, then circuit density is increased, but light diffraction causes significant pattern deformation

Engineering Contradiction:
Improvecircuit densityVSAvoidpattern accuracy
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent changes the parameters of connection patterns through optical proximity correction, modifying dimensions, pitches, and shapes to compensate for anticipated diffraction effects. By adjusting these parameters in the mask design phase, patterns that would normally deform due to light diffraction are pre-corrected to achieve the desired final pattern accuracy, enabling higher circuit density without sacrificing manufacturing precision

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies preliminary anti-action by introducing opposite corrections to counteract the harmful diffraction effects before they occur. The OPC process calculates and applies reverse deformations to the mask patterns that will compensate for the expected light diffraction during exposure, thereby preventing pattern deformation and maintaining manufacturing precision even with high-density patterns

Inventive Principle:
Principle #9Preliminary anti-action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the quality of photomasks and semiconductor structures by ensuring accurate pattern formation and improved electrical connections, addressing the limitations of DPT in overlay control and alignment.

Implementation Method 1

prevent the connection patterns with dimensions and/or pitches that violates the predetermined rule of photolithography, from causing significant light diffraction during fabricating corresponding patterns of photomask

Methodology Applied
Scientific EffectLight diffraction: Diffraction

Data Source

PatentUS12147156B2Method of fabricating a semiconductor layout and a semiconductor structure
Publication Date: 2024.11.19 FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
  • US12147156B2 patent drawing
  • US12147156B2 patent drawing
  • US12147156B2 patent drawing

AI summary

The present disclosure discloses a method of fabricating a semiconductor layout comprising the following steps. A layout is provided, and the layout includes a plurality of connection patterns. The connection patterns are decomposed to a plurality of first connection patterns and a plurality of second connection patterns alternatively arranged with each other. An optical proximity correction process is performed on the first connection patterns and the second connection patterns to form a plurality of third connection patterns and a plurality of fourth connection patterns, wherein at least a portion of the third connection patterns is overlapped with the fourth connection patterns. The third connection patterns and the fourth connection patterns are outputted to form photomasks. Accordingly, the quality of the photomask may be improved, and the photomask may therefore include more accurate patterns and contours. The present disclosure also provides a method of fabricating a semiconductor structure.