Semiconductor Electrode Layout Pre-Distortion for OPE Control
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Solution Overview
Problem
Existing photolithographic processes in semiconductor manufacturing suffer from optical proximity effects (OPEs) that cause shape distortions in semiconductor devices, which are typically mitigated post-layout using optical proximity correction (OPC).
Innovation Solution
Pre-distort layout diagrams by widening the middle region of line patterns in anticipation of etching, specifically by making the middle region of bridge segments wider than other parts of the line pattern, to mitigate over-etch distortions during the design phase rather than relying solely on OPC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If optical proximity correction (OPC) is applied after layout generation, then shape distortions caused by optical proximity effects are mitigated, but the manufacturing process complexity and time are increased
Solution Approach 1:
The patent applies pre-distortion to the layout diagram before the photolithographic process, proactively compensating for expected etching distortions. By widening the middle region of line patterns in advance, the final etched shape achieves the desired dimensions without requiring post-layout OPC, thus reducing process complexity while maintaining shape accuracy
Solution Approach 2:
The patent introduces a preliminary counter-action by deliberately distorting the layout diagram in the opposite direction of expected etching distortion. The middle region of line patterns is widened beforehand to compensate for the anticipated narrowing during etching, thereby pre-neutralizing the harmful optical proximity effects before they occur in the actual manufacturing process
2Manufacturing precision
If OPC is used to correct layout distortions, then manufacturing precision is improved, but the production time and productivity are reduced
Solution Approach 1:
The pre-distortion of the layout diagram is performed during the design phase rather than during the manufacturing process. By pre-calculating and applying the necessary compensations to the layout data before fabrication begins, the patent eliminates the need for time-consuming OPC operations during production, thereby maintaining shape accuracy while significantly reducing production time and improving overall productivity
3Manufacturing precision
If the middle region of line patterns is widened in the layout diagram, then over-etch distortions are reduced, but the layout design complexity is increased
Solution Approach 1:
The patent applies the pre-distortion technique selectively to specific regions of the layout diagram, namely the middle regions of line patterns that are susceptible to over-etch distortions. Rather than uniformly modifying the entire layout, only the vulnerable segments are widened, thereby achieving improved etch accuracy while minimizing the increase in overall layout design complexity
Data Source
AI summary
A semiconductor structure includes a doped region extending in a first direction. The semiconductor structure further includes an electrode extending in a second direction perpendicular to the first direction. The electrode includes a first segment over the doped region; an extension extending beyond the doped region, wherein the extension has a uniform width in the first direction, and a conductive element, wherein a width of the conductive element in the first direction increases as a distance from the extension increases along an entirety of the conductive element in the second direction.