Semiconductor Layout Splitting for Double-Patterning Overlay Errors

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The double patterning technique (DPT) faces challenges with overlay control and alignment issues, leading to disconnection or connection problems in semiconductor fabrication, particularly when high-density circuit patterns are decomposed into lower density sets, resulting in open or short circuits.

Innovation Solution

A method involving the decomposition of semiconductor layouts into first and second connection patterns, with a to-be-split pattern split into cutting and counterpart cutting portions, and forming photomasks with modified cutting portions to ensure accurate alignment and prevent disconnections, using larger areas for these portions to form a merged pattern that supports contact structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If double patterning technique is used to fabricate high-density circuit patterns, then the minimum pattern distance can be enlarged beyond photolithography limits, but overlay control and alignment issues worsen, leading to disconnection or connection problems

Engineering Contradiction:
Improveminimum pattern distanceVSAvoidoverlay control and alignment
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent divides the high-density circuit pattern into two separate low-density circuit patterns that can be fabricated using standard photolithography. By segmenting the original pattern into first and second low-density patterns, each pattern can be formed with better overlay control and alignment, avoiding the disconnection and connection problems that occur when directly patterning high-density circuits beyond the photolithography resolution limit.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If high-density circuit patterns are decomposed into lower density sets, then the pattern can be fabricated with current mask aligners, but overlay errors and inaccurate alignment occur more frequently

Engineering Contradiction:
Improvepattern fabrication capabilityVSAvoidoverlay errors and alignment accuracy
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent introduces a merged pattern as an intermediary structure that connects the first and second low-density circuit patterns. This merged pattern acts as a mediator that ensures proper electrical connection between the segmented patterns while maintaining the overall high-density circuit functionality. The merged pattern is specifically designed to prevent disconnection issues that arise from overlay errors during the decomposition process.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If multiple exposure processes are used in double patterning, then high-density patterns can be formed, but the complexity of overlay control and alignment increases significantly

Engineering Contradiction:
Improvehigh-density pattern formationVSAvoidoverlay control and alignment complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the high-density pattern fabrication into distinct stages: first forming low-density patterns with standard photolithography, then adding the merged pattern structure. This segmentation reduces the complexity of overlay control by breaking down the multiple exposure process into manageable steps, where each step has simpler alignment requirements compared to direct high-density patterning.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The merged pattern serves as an intermediary structure that simplifies the overall fabrication complexity. By introducing this intermediate merged pattern layer, the patent reduces the burden of overlay control in subsequent processing steps, as the merged pattern provides a stable reference structure that facilitates easier alignment for forming the final high-density circuit patterns.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12381082B2Semiconductor structure, method for fabricating thereof, and method for fabricating semiconductor layout
Publication Date: 2025.08.05 FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
  • US12381082B2 patent drawing
  • US12381082B2 patent drawing
  • US12381082B2 patent drawing

AI summary

A method for fabricating a semiconductor structure includes the following steps. Decomposing a layout to first connection patterns and second connection patterns alternatively arranged with each other, where a to-be-split pattern is disposed between the first connection pattern and the second connection pattern; splitting the to-be-split pattern into a cutting portion and a counterpart cutting portion; forming a first photomask having a layout constructed by the first connection pattern and the cutting portion; forming a second photomask having a layout constructed by the second connection pattern and the counterpart cutting portion; transferring layouts of the first and second photomasks to a target layer to form connection patterns and a merged pattern, where the contour of the merged pattern is defined by the cutting portion and the counterpart cutting portion, and each end surface of the merged pattern comprises a recessed region and a protruded region.